NDLI: A new scalable VLSI architecture for Reed-Solomon decoders

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MDSP-II: 16-bit DSP with mobile communication accelerator

A single chip DMT modem for high-speed WLANS

A new scalable VLSI architecture for Reed-Solomon decoders

An embedded stack microprocessor for SDH telecommunication applications

CMOS technology characterization for analog and RF design

Nano-amp, active-bulk, weak-inversion analog circuits

Current sensor IC provides 9 bit+sign result without external sense resister

On the exact design of RF oscillators

Phase noise and timing jitter in oscillators

Phase noise in multi-gigahertz CMOS ring oscillators

Nonlinear behavioral modeling and phase noise evaluation in phase locked loops

Microwave CMOS-devices and circuits

Broadband, 0.25 /spl mu/m CMOS LNAs with sub-2dB NF for GSM applications

1 GHz programmable analog phase shifter for adaptive antennas

A 10 mW inductorless, broadband CMOS low noise amplifier for 900 MHz wireless communications

A 1.5 V, wide band 3 GHz, CMOS quadrature direct up-converter for multi-mode wireless communications

Integration architecture for system-on-a-chip design

Synthesis of interface controllers from timing diagram specifications

On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rule

The virtual chip set: a parametric IP library for system-on-a-chip design

Complete mixed-signal building blocks for single-chip GSM baseband processing

A novel CPLD based implementation of a motion detection algorithm for surveillance applications

An energy conscious methodology for early design exploration of heterogeneous DSPs

DSP16000: a high performance, low-power dual-MAC DSP core for communications applications

A single-chip low power DSP/RISC CPU with 0.25 /spl mu/m CMOS technology

A 9.5 mW 330 /spl mu/sec 1024-point FFT processor

Design and implementation of a 1024-point pipeline FFT processor

A 1 V, 25 /spl mu/W speech recognizer for portable systems

CMOS-year 2010 and beyond; from technological side

Impact of high resolution lithography on IC mask design

A new optimization strategy for CMOS device process in the era of 0.2 /spl mu/m and beyond for MPU's and ASIC's

A merged 2.5 V and 3.3 V 0.25-/spl mu/m CMOS technology for ASICs

Laser formed connections for programmable wiring

A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications

Towards one chip HDTV MPEG2 encoder LSI

An ultra low power variable length decoder for MPEG-2 exploiting codeword distribution

A system LSI utilizing media processor core "MMA"

A single chip AV decoder for the DVD player adopting the MCP architecture

Architecture and implementation of a bitserial sorter for weighted median filtering

Implementation of H.324 audiovisual codec for mobile computing

A simple algorithm for calculating frequency-dependent inductance bounds

Nonlinear macromodels of large coupled interconnect networks

How to make theoretically passive reduced-order models passive in practice

Efficient full-wave simulation in layered, lossy media

Systematic calibration of AC MOSFET model parameters including non-quasi-static effect

High-frequency application of MOS compact models and their development for scalable RF model libraries

Modified mismatch-shaping for continuous-time delta-sigma modulators

A 13 bit, 1.4 MS/s, 3.3 V sigma-delta modulator for RF baseband channel applications

A 150 MHz 13b 12.5 mW IF digitizer

A Nyquist rate pixel level ADC for CMOS image sensors

Video-rate D/A converter using reduced rate sigma-delta modulation

A 325 MHz 3.3 V 10-bit CMOS D/A converter core with novel latching driver circuit

A 12 bit 200 MHz low glitch CMOS D/A converter

A low power, high performance, 960 macrocell, SRAM based complex PLD

Computational field programmable architecture

A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability

Implementing logic in FPGA embedded memory arrays: architectural implications

A silicon efficient FLEX 6000 programmable logic architecture

A current-mode based field programmable analog array architecture for signal processing applications

Re-inventing the DRAM for embedded use: a compiled, wide-databus DRAM macrocell with high bandwidth and low power

A DRAM module generator with an expandable cell array scheme

Hole filling: a novel delay reduction technique using selector logic

Hierarchical watermarking in IC design

FPGA fingerprinting techniques for protecting intellectual property

An overview of library characterization in semi-custom design

A new algorithm for computing the "effective capacitance" in deep sub-micron circuits

Timing qualification of a 0.25-/spl mu/m CMOS ASIC library using BSIM3 FET models

Manufacturability analysis of standard cell libraries

A CMOS cell generation system for two-dimensional transistor placement

Standard cell power IC design

Design considerations for gigabit Ethernet 1000Base-T twisted pair transceivers

A 3.3 V analog adaptive line-equalizer for fast Ethernet data communication

A 10-Gbps 83 mW GaAs HBT equalizer/detector for coaxial cable channels

A dual-channel QAM/QPSK receiver IC with integrated cable set-top box functionality

1.5 watt 622/155 Mbps single chip for full ATM-SDH/SONET physical layer in 0.5 /spl mu/m BiCMOS 3.3 V

A multistage amplifier topology with embedded tracking compensation

A 120 MHz, 12 mW CMOS current feedback opamp

A CMOS instrumentation amplifier with 600 nV offset, 8.5 nV//spl radic/(Hz) noise and 150 dB CMRR

A 1.8 V pseudo-differential switched-capacitor amplifier

A high-speed BiCMOS switched-current track-and-hold circuit

An open-loop full CMOS 103 MHz -61 dB THD S/H circuit

Architectures and circuits for RF CMOS receivers

A high Q 200 MHz low-power fully integrated bandpass IF filter

A VLSI low power solution for mobile satellite radio receivers

Silicon germanium and silicon bipolar RF circuits for 2.7 V single chip radio transceiver integration

A 0.25 /spl mu/m CMOS transceiver front-end for GSM

An automatic offset compensation technique applicable to existing operational amplifier core cell

A baseband integrated circuit for homodyne cordless phones

A 3-V high-bandwidth integrator for magnetic disk read channel continuous-time filtering applications

Ferroelectric nonvolatile memories for embedded applications

An embedded FeRAM macro cell for a smart card microcontroller

Modeling and simulation for low power in mixed-signal integrated systems

MPDE methods for efficient analysis of wireless systems

Practical timing analysis of asynchronous circuits using time separation of events

Simulator for switched-current integrated circuits

Efficient derivation of exact s-expanded symbolic expressions for behavioral modeling of analog circuits

Transforming small-signal modeling into control system modeling

Behavioral model for D/A converters as VSI virtual components

Automated design of switched-current cells

Schematic driven module generation for analog circuits with performance optimization and matching considerations

Mondriaan: a tool for automated layout synthesis of array-type analog blocks

Oscillator jitter due to supply and substrate noise

A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

A low-power 16-bit multiplier-accumulator using series-regulated mixed swing techniques

A 1.3 V low-power 430 MHz front-end using a standard digital CMOS process [ISM wireless link]

Estimation of average switching power under accurate modeling of signal correlations

The direct skew detect synchronous mirror delay (Direct SMD) for ASICs

VCOs with very low sensitivity to noise on the power supply

Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability

Design in hot-carrier reliability for high performance logic applications

Performance and reliability of asymmetric LDD devices and logic gates

Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology

Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection

Simultaneous switching noise analysis and low bouncing buffer design [CMOS ICs]

On-chip analog signal generator for mixed-signal built-in self-test

RF-CMOS oscillators with switched tuning

A 2.7 V 900 MHz/1.9 GHz dual-band transceiver IC for digital wireless communication

A 2 V 1.6 GHz BJT phase-locked loop

A 1 GHz, low-phase-noise CMOS frequency synthesizer with integrated LC VCO for wireless communications

A 1.8 V/3.5 mA 1.1 GHz/300 MHz CMOS dual PLL frequency synthesizer IC for RF communications

2.488 Gb/s silicon bipolar clock and data recovery IC for SONET (OC-48)

Issues for fabless design companies moving towards deep submicron system on a chip design

Reducing switching activity on datapath buses with control-signal gating

A new direction in ASIC high-performance clock methodology

A nonlinear programming and local improvement method for standard cell placement

A new router for reducing "antenna effect" in ASIC design

Combined transistor sizing with buffer insertion for timing optimization

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)

Proceedings of CICC 97 - Custom Integrated Circuits Conference

Proceedings of Custom Integrated Circuits Conference

Proceedings of the IEEE 1995 Custom Integrated Circuits Conference

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03222 282435
Mail: ndl-support@iitkgp.ac.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in