NDLI: All-digital PLL and GSM/EDGE transmitter in 90nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Staszewski, R.B. Wallberg, J. Rezeq, S. Chih-Ming Hung Eliezer, O. Vemulapalli, S. Fernando, C. Maggio, K. Staszewski, R. Barton, N. Meng-Chang Lee Cruise, P. Entezari, M. Muhammad, K. Leipold, D.
Copyright Year	2005
Description	Author affiliation: Texas Instruments, Dallas, TX, USA (Staszewski, R.B.; Wallberg, J.; Rezeq, S.; Chih-Ming Hung; Eliezer, O.; Vemulapalli, S.; Fernando, C.; Maggio, K.; Staszewski, R.; Barton, N.; Meng-Chang Lee; Cruise, P.; Entezari, M.; Muhammad, K.; Leipold, D.)
Abstract	A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS. It transmits GMSK with 0.5/spl deg/ rms phase error and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time. A digitally controlled 6dBm class-E PA modulates the amplitude and meets the EDGE spectral mask with 3.5% EVM.
Sponsorship	IEEE Solid-State Circuits Soc. IEEE San Francisco Sect. Bay Area Council Univ. of PA
Starting Page	316
Ending Page	600
File Size	522102
Page Count	285
File Format	PDF
ISBN	0780389042
ISSN	01936530
DOI	10.1109/ISSCC.2005.1493996
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-02-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops GSM IIR filters Varactors CMOS process Frequency modulation Radio transmitters CMOS digital integrated circuits CMOS analog integrated circuits Land mobile radio cellular systems
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Electronic, Optical and Magnetic Materials

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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