NDLI: Session 1 overview - plenary session

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2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

2012 IEEE International Solid-State Circuits Conference

2011 IEEE International Solid-State Circuits Conference

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.

Foreword - entering the nanoelectronic integrated-circiut era

Table of contents

SE1 power line lan: is there a concrete wall dividing wireless from wireline?

SE2 when processors hit the power wall (or "when the CPU hits the fan")

SE3 integration in the 3rd dimension: opportunities and challenges

Session 1 overview - plenary session

Nanoelectronics for an ubiquitous information society

Ambient intelligence: gigascale dreams and nanoscale realities

Integration and innovation in the nanoelectronics era

Session 2 overview - non-volatile memory

A 146 mm/sup 2/ 8 Gb NAND flash memory with 70 nm CMOS technology

An 8 Gb multi-level NAND flash memory with 63 nm STI CMOS process technology

Enhanced write performance of a 64 Mb phase-change random access memory

A 128 Mb NOR flash memory with 3 MB/s program time and low-power write performance by using in-package inductor charge-pump

A 125 MHz burst-mode flexible read-while-write 256 Mbit 2b/c 1.8V NOR flash memory

A 90 nm 512 Mb 166 MHz multilevel cell flash memory with 1.5 MByte/s programming

A 126 mm/sup 2/ 4 Gb multilevel AG-AND flash memory with 10 MB/s programming throughput

Session 3 overview - backplane transceivers

A 5Gb/s NRZ transceiver with adaptive equalization for backplane transmission

A 6.4Gb/s CMOS SerDes core with feedforward and decision-feedback equalization

A 0.6 to 9.6Gb/s binary backplane transceiver core in 0.13/spl mu/m CMOS

A transmit architecture with 4-tap feedforward equalization for 6.25/12.5Gb/s serial backplane communications

A 6.25Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications

12Gb/s duobinary signaling with /spl times/2 oversampled edge equalization

A 25Gb/s PAM4 transmitter in 90nm CMOS SOI

Session 4 overview - mixed-domain systems

Joining ionics and electronics: semiconductor chips with ion channels, nerve cells, and brain tissue

An analog bionic ear processor with zero-crossing detection

An IC/microfluidic hybrid microsystem for 2D magnetic manipulation of individual biological cells

A VLSI analog computer/math co-processor for a digital computer

Towards chip-scale atomic clocks

Opportunities for optics in integrated circuits applications

Processing of MEMS gyroscopes on top of CMOS ICs

Session 5 overview - WLAN transceivers

An auto-I/Q calibrated CMOS transceiver for 802.11 g

An 802.11g WLAN SoC

A fully integrated SoC for 802.11b in 0.18 /spl mu/m CMOS

A compact dual-band direct-conversion CMOS transceiver for 802.11a/b/g WLAN

A low-power dual-band triple-mode WLAN CMOS transceiver

A system-on-chip for bi-directional point-to-multipoint wireless digital audio applications

A dual-band frequency synthesizer for 802.11a/b/g with fractional-spur averaging technique

A fully integrated transformer-based front-end architecture for wireless transceivers

Session 6 overview - high-speed and oversampled DACs

A 1.2GS/s 15b DAC for precision signal generation

A 1.6GS/s 12b return-to-zero GaAs RF DAC for multiple Nyquist operation

A 1.7GHz 3V direct digital frequency synthesizer with an on-chip DAC in 0.35 /spl mu/m SiGe BiCMOS

A 12b 500MS/s DAC with >70dB SFDR up to 120MHz in 0.18μm CMOS

A 350MHz low-OSR /spl Delta//spl Sigma/ current-steering DAC with active termination in 0.13 /spl mu/m CMOS

Integrated stereo delta-sigma class D amplifier

A 22GS/s 6b DAC with integrated digital ramp generator

A 2GHz mean-square power detector with integrated offset chopper

Session 7 overview - multimedia processing

A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications

An 81 MHz, 1280 /spl times/ 720pixels /spl times/ 30frames/s MPEG-4 video/audio CODEC processor

An H.264/MPEG-4 audio/visual CODEC LSI with module-wise dynamic voltage/frequency scaling

A streaming processing unit for a CELL processor

A 600MIPS 120mW 70/spl mu/A leakage triple-CPU mobile application processor chip

90nm low leakage SoC design techniques for wireless applications

A 100-channel analog CMOS auditory filter bank for speech recognition

E1 mobile imaging: paradigm shift or technology bubble?

E2 what papers will and will not be at ISSCC 2010?

SE4 toward the nanoscale transistor highlights of 2004 symposium on VLSI technology

Session 8 overview - circuits for high-speed links and clock generators

Circuit techniques for a 40Gb/s transmitter in 0.13/spl mu/m CMOS

40Gb/s 4:1 MUX/1:4 DEMUX in 90nm standard CMOS

An 80GHz travelling-wave amplifier in a 90nm CMOS technology

A 1.8V three-stage 25GHz 3dB-BW differential non-uniform downsized distributed amplifier

A 1V 24GHz 17.5mW PLL in 0.18/spl mu/m CMOS

Spread-spectrum clock generator for serial ATA using fractional PLL controlled by /spl Delta//spl Sigma/ modulator with level shifter

A low-jitter 5000ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18/spl mu/m CMOS

Session 9 overview - switched-capacitor delta-sigma modulators

A 0.6V 82dB /spl Delta//spl Sigma/ audio ADC using switched-RC integrators

A low-power multi-bit /spl Delta//spl Sigma/ modulator in 90nm digital CMOS without DEM

A 66dB DR 1.2V 1.2mW single-amplifier double-sampling 2/sup nd/-order /spl Delta//spl Sigma/ ADC for WCDMA in 90nm CMOS

A 100dB SNR 2.5MS/s output data rate /spl Delta//spl Sigma/ ADC

An 80MHz 4/spl times/ oversampled cascaded /spl Delta//spl Sigma/-pipelined ADC with 75dB DR and 87dB SFDR

A 106dB SNR hybrid oversampling ADC for digital audio

A 0.18/spl mu/m 102dB-SNR mixed CT SC audio-band /spl Delta//spl Sigma/ ADC

Session 10 overview - microprocessors and signal processing

The implementation of a 2-core multi-threaded Itanium/spl reg/-family processor

The design and implementation of a first-generation CELL processor

Implementation of a 4/sup th/-generation 1.8GHz dual-core SPARC V9 microprocessor

Creating the BlueGene/L supercomputer from low-power SoC ASICs

An SoC with 1.3 Gtexels/s 3D graphics full pipeline engine for consumer applications

A 50 Mvertices/s graphics processor with fixed-point programmable vertex shader for mobile applications

A 51.2 GOPS 1.0 GB/s-DMA single-chip multi-processor integrating quadruple 8-way VLIW processors

XiSystem: a XiRisc-based SoC with a reconfigurable IO module

Session 11 overview - ultra wideband solutions

An interference robust receive chain for UWB radio in SiGe BiCMOS

A SiGe BiCMOS 1ns fast hopping frequency synthesizer for UWB radio

A 7-band 3-8 GHz frequency synthesizer with 1 ns band-switching time in 0.18 /spl mu/m CMOS technology

A regenerative semi-dynamic frequency divider for mode-1 MB-OFDM UWB hopping carrier generation

A 3.1 to 8.2 GHz direct conversion receiver for MB-OFDM UWB communications

A 1.4V 5GHz four-antenna Cartesian-combining receiver in 90nm CMOS for beamforming and spatial diversity applications

A 24 GHz phased-array transmitter in 0.18 /spl mu/m CMOS

A 3.1 to 5 GHz CMOS DSSS UWB transceiver for WPANs

A 0.13 /spl mu/m CMOS UWB transceiver

Session 12 overview - optical communications

A 3 V 10.7 Gb/s differential laser diode driver with active back-termination output stage

A 20 Gb/s VCSEL driver with pre-emphasis and regulated output impedance in 0.13 /spl mu/m CMOS

A 0.5 /spl mu/m SiGe pre-equalizer for 10 Gb/s single-mode fiber optic links

1.25 Gb/s burst-mode receiver ICs with quick response for PON systems

A 10 Gb/s burst-mode CDR IC in 0.13 /spl mu/m CMOS

A 12.5 Mb/s to 2.7 Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback

A 3.125 Gb/s limit amplifier with 42 dB gain and 1 /spl mu/s offset compensation in 0.18 /spl mu/m CMOS

A 21 mW 2.5 Gb/s 15 k/spl Omega/ self-compensated differential transimpedance amplifier

Session 13 overview - sensors

A CMOS temperature sensor with a 3/spl sigma/ inaccuracy of /spl plusmn/0.1/spl deg/C from -55/spl deg/C to 125/spl deg/C

A CMOS rotary encoder system based on magnetic pattern analysis with a resolution of 10b per rotation

A Hall sensor analog front end for current measurement with continuous gain calibration

A microsystem for trace environmental monitoring

A fully integrated CMOS Hall sensor with a 3.65 /spl mu/T 3/spl sigma/ offset for compass applications

A 0.8 mA 50 Hz 15 b SNDR /spl Delta//spl Sigma/ closed-loop 10g accelerometer using an 8/sup th/-order digital compensator

A 200/spl times/160 pixel CMOS fingerprint recognition SoC with adaptable column-parallel processors

A CMOS integrated capacitive fingerprint sensor with 32b microcontroller

Session 14 overview - low-power wireless and advanced integration

A 950 MHz rectifier circuit for sensor networks with 10 m-distance

A 1 V 433/868 MHz 25 kb/s-FSK 2 kb/s-OOK RF transceiver SoC in standard digital 0.18 /spl mu/m CMOS

Nano-wires for room temperature operated hybrid CMOS-NANO integrated circuits

A 3D integration scheme utilizing wireless interconnections for implementing hyper brains

A 195Gb/s 1.2W 3D-stacked inductive inter-chip wireless superconnect with transmit power control scheme

Substrate integrity beyond 1 GHz

Design for manufacturability in nanometer era: system implementation and silicon results

A 20 GHz CMOS RF down-converter with an on-chip antenna

A flexible 8b asynchronous microprocessor based on low-temperature poly-silicon TFT technology

Session 15 overview - ADCs, DC references, and converters

A split-ADC architecture for deterministic digital background calibration of a 16b 1 MS/s ADC

A 3.3 mW 12 MS/s 10b pipelined ADC in 90 nm digital CMOS

A 50 MS/s (35 mW) to 1 kS/s (15 /spl mu/W) power scaleable 10b pipelined ADC with minimal bias current variation

A 10 b 125 MS/s 40 mW pipelined ADC in 0.18 /spl mu/m CMOS

A 30mW 8b 200MS/s pipelined CMOS ADC using a switched-opamp technique

A 0.5/spl mu/A precision CMOS floating-gate analog reference

A SC DC-DC converter with pseudo-continuous output regulation using a three-stage switchable opamp

Session 16 overview - clock distribution and power management

Clock distribution on a dual-core, multi-threaded Itanium/sup /spl reg//-family processor

A 90nm variable-frequency clock system for a power-managed Itanium/sup /spl reg//-family processor

Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multi-core SoCs

High-tension power delivery: operating 0.18 /spl mu/m CMOS digital logic at 5.4V

Ultra-dynamic voltage scaling using sub-threshold operation and local voltage dithering in 90nm CMOS

Sleep transistor circuits for fine-grained power switch-off with short power-down times

Power and temperature control on a 90nm Itanium/sup /spl reg//-family processor

Session 17 overview - RF cellular ICs

A 90nm CMOS single-chip GPS receiver with 5dBm out-of-band IIP3 2.0dB NF

A single-chip Si-LDMOS power amplifier for GSM

A 1.75GHz GSM/EDGE polar modulated CMOS RF power amplifier

A loop-bandwidth calibration system for fractional-N synthesizer and /spl Delta//spl Sigma/-PLL transmitter

All-digital PLL and GSM/EDGE transmitter in 90nm CMOS

A single-chip quad-band GSM/GPRS transceiver in 0.18 /spl mu/m standard CMOS

A CMOS direct down-converter with +78dBm minimum IIP2 for 3G cell-phones

A 5/sup th/-order continuous-time harmonic-rejection G/sub m/C filter with in-situ calibration for use in transmitter applications

A fully-integrated highly linear zero-IF CMOS cellular CDMA receiver

Session 18 overview - high-speed interconnects and building blocks

A 10Gb/s CMOS adaptive equalizer for backplane applications

A 7-tap transverse analog-FIR filter in 0.12 /spl mu/m CMOS for equalization of 10Gb/s fiber-optic data systems

A 10Gb/s eye-opening monitor in 0.13 /spl mu/m CMOS

A 100mW 4/spl times/10Gb/s transceiver in 80nm CMOS for high-density optical interconnects

A 0.25 /spl mu/m CMOS 3b 12.5 GS/s frequency channelized receiver for serial-links

An RF/baseband FDMA-interconnect transceiver for reconfigurable multiple access chip-to-chip communication

A 40 Gb/s 2.5 V 2/sup 7/-1 PRBS generator in SiGe using a low-voltage logic family

A 72 Gb/s 2/sup 31/-1 PRBS generator in SiGe BiCMOS technology

Session 19 overview - imagers

A 1/4.5in 3.1M pixel FT-CCD with 1.56 /spl mu/m pixel size for mobile applications

A 2.0 /spl mu/m pixel pitch MOS image sensor with an amorphous Si film color filter

A 19.5b dynamic range CMOS image sensor with 12b column-parallel cyclic A/D converters

A 100 dB dynamic range CMOS image sensor using a lateral overflow integration capacitor

A linear-logarithmic CMOS sensor with offset calibration using an injected charge signal

Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

A progressive 1920/spl times/1080 imaging system-on-chip for HDTV cameras

A high-speed, profile data acquiring image sensor

Temporal change threshold detection imager

A single photon detector array with 64/spl times/64 resolution and millimetric depth accuracy for 3D imaging

SE5 - SRAM design in the nanoscale era

E3 RF MEMS: fact or stiction

E4 Driving miss ubiquity: what applications will fill tomorrows fabs?

Session 20 overview - processor building blocks

An 8GHz floating-point multiply

A 110GOPS/W 16b multiplier and reconfigurable PLA loop in 90nm CMOS

A double-precision multiplier with fine-grained clock-gating support for a first-generation CELL processor

A low-leakage 2.5GHz skewed CMOS 32b adder for nanometer CMOS technologies

The multi-threaded, parity-protected 128-word register files on a dual-core Itanium/sup /spl reg//-family processor

A 32b 64-word 9-read-port/7-write-port pseudo dual-bank register file using copied memory cells for a multi-threaded processor

A 3Gb/s/ch transceiver for RC-limited on-chip interconnects

Session 21 overview - RF trends: above-IC integration and mm-wave

Tunable RF and analog circuits using on-chip MEMS passive components

Integration of high-Q BAW resonators and filters above IC

A SiGe:C BiCMOS WCDMA zero-IF RF front-end using an above-IC BAW filter

A 400 /spl mu/W-RX, 1.6mW-TX super-regenerative transceiver for wireless sensor networks

Thin-film as enabling passive integration technology for RF SoC and SiP

A 60GHz direct-conversion CMOS receiver

A 70GHz cascaded multi-stage distributed amplifier in 90nm CMOS technology

A 114GHz VCO in 0.13 /spl mu/m CMOS technology

A fully integrated BiCMOS PLL for 60 GHz wireless applications

Session 22 overview - PLLs, DLLs and VCOs

0.94ps-rms-jitter 0.016mm/sup 2/ 2.5GHz multi-phase generator PLL with 360/spl deg/ digitally programmable phase shift for 10Gb/s serial links

A 15mW 3.125GHz PLL for serial backplane transceivers in 0.13 /spl mu/m CMOS

A low-jitter wideband multiphase PLL in 90nm SOI CMOS technology

A 44GHz differentially tuned VCO with 4GHz tuning range in 0.12 /spl mu/m SOI CMOS

A low-phase-noise 0.004ppm/step DCXO with guaranteed monotonicity in 90nm CMOS

A self-biased PLL with current-mode filter for clock generation

An ultra-low-power fast-lock-in small-jitter all-digital DLL

Session 23 overview - wireless receivers for consumer applications

A direct-conversion receiver for DVB-H

UMTV: a single chip TV receiver for PDAs, PCs, and cell phones

A 0.12 /spl mu/m CMOS DVB-T tuner

A CMOS TV tuner/demodulator IC with digital image rejection

A compact triple-band Eureka-147 RF tuner with an FM receiver

A 2.3GHz SiGe RFIC front-end for U.S. satellite radio applications

A single-chip receiver for multi-user low-noise block down-converters

Session 24 overview - baseband processing

A 1.2V 6.7mW impulse-radio UWB baseband transceiver

A 480Mb/s LDPC-COFDM-based UWB baseband transceiver

A 135Mb/s DVB-S2 compliant codec based on 64800b LDPC and BCH codes

A reprogrammable EDGE baseband and multimedia handset SoC with 6 Mb embedded DRAM

A multi-standard DSL central office modem SoC

A WLAN SoC for video applications including beamforming and maximum ratio combining

A 180MS/s, 162Mb/s wideband three-channel baseband and MAC processor for 802.11 a/b/g

Session 25 overview - dynamic memory

An 18.5ns 128MB SOI DRAM with a floating body cell

A 322MHz random-cycle embedded DRAM with high-accuracy sensing and tuning

A 400MHz random-cycle dual-port interleaved DRAM with striped-trench capacitor

An AND-type match-line scheme for energy-efficient content addressable memories

Concordant memory design using statistical integration for the billions-transistor era

A 800Mb/s/pin 2GB DDR2 SDRAM using an 80nm triple metal technology

A 20GB/s 256MB DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter

Session 26 overview - SRAM memory

A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply

A 256MB synchronous-burst DDR SRAM with hierarchical bit-line architecture for mobile applications

A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications

Low-power embedded SRAM modules with expanded margins for writing

PVT-aware leakage reduction for on-die caches with improved read stability

0.3 to 1.5V embedded SRAM with device-fluctuation-tolerant access-control and cosmic-ray-immune hidden-ECC scheme

A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a CELL processor

The asynchronous 24MB on-chip level-3 cache for a dual-core Itanium/sup /spl reg//-family processor

Session 27 overview - filters and continuous-time /spl Delta//spl Sigma/ converters

A 3mW 74dB SNR 2MHz CT /spl Delta//spl Sigma/ ADC with a tracking-ADC-quantizer in 0.13 /spl mu/m CMOS

A 1.2V 3.5mW /spl Delta//spl Sigma/ modulator with a passive current summing network and a variable gain function

A 4/sup th/-order 86dB CT /spl Delta//spl Sigma/ ADC with two amplifiers in 90nm CMOS

A low-noise low-voltage CT /spl Delta//spl Sigma/ modulator with digital compensation of excess loop delay

A 4.7mW 89.5dB DR CT complex /spl Delta//spl Sigma/ ADC with built-in LPF

A 43mW CT complex /spl Delta//spl Sigma/ ADC with 23MHz of signal bandwidth and 68.8dB SNDR

Dynamically power-optimized channel-select filter for zero-IF GSM

A 0.5V filter with PLL-based tuning in 0.18 /spl mu/m CMOS

Session 28 overview - clocking and I/O

A sub-10ps multi-phase sampling system using redundancy

A programmable on-chip picosecond jitter-measurement circuit without a reference-clock input

A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery

A CMOS DLL-based 120MHz to 1.8GHz clock generator for dynamic frequency scaling

1.1 to 1.6GHz distributed differential oscillator global clock network

A 3Gb/s 8b single-ended transceiver for 4-drop DRAM interface with digital calibration of equalization skew and offset coefficients

3Gb/s AC-coupled chip-to-chip communication using a low-swing pulse receiver

Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3/spl times/V/sub DD/ input tolerance by using 1/spl times/V/sub DD/ devices and single V/sub DD/ supply

Clocking and circuit design for a parallel I/O on a first-generation CELL processor

Session 29 overview - RF techniques

A 21 to 26GHz SiGe bipolar PA MMIC

Direct-digital RF modulator IC in 0.13 /spl mu/m CMOS for wide-band multi-radio applications

Low-power g/sub m/-boosted LNA and VCO circuits in 0.18 /spl mu/m CMOS

A 0.75 to 2.2GHz continuously-tunable quadrature VCO

A 32 GHz quadrature LC-VCO in 0.25 /spl mu/m SiGe BiCMOS technology

A 1mW current-reuse CMOS differential LC-VCO with low phase noise

I/Q mismatch compensation in a 90nm low-IF CMOS receiver

A noise cancellation technique in active RF-CMOS mixers

A WLAN direct up-conversion mixer with automatic image rejection calibration

A 17mW 0.66mm/sup 2/ direct-conversion receiver for 1 Mb/s cable replacement

Session 30 overview - displays and biosensors

A CMOS-based microdisplay with calibrated backplane

A panel-sized TFT-LCD scan driver

An LCD column driver using a switch capacitor DAC

A three-dimensional neural recording microsystem with implantable data compression circuitry

A battery-powered 8-channel wireless FM IC for biopotential recording applications

A wireless biosensing chip for DNA detection

A programmable electrochemical biosensor array in 0.18 /spl mu/m standard CMOS

Session 31 overview - mass storage

A CMOS 1X- to 16X-Speed DVD write channel IC

DLL-based clock recovery in a PRML channel

A CMOS multi-format read/write SoC for 7/spl times/Blu-ray/16/spl times/DVD/56/spl times/CD

Session 32 overview - advanced array structures

Memory technologies in the nano-era: challenges and opportunities

A flexible 240/spl times/320-pixel display with integrated row drivers manufactured in organic electronics

A sheet-type scanner based on a 3D stacked organic-transistor circuit with double word-line and double bit-line structure

ISSCC 2005 tutorials

RF circuit design from technology to systems

Index to authors

Executive Committee

Program Committee

San francisco marriott hotel location map

ISSCC 2006 call for papers

Timetable of ISSCC 2005 sessions

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)

2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278)

1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156)

1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

Proceedings ISSCC '95 - International Solid-State Circuits Conference

Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94

1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers

1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers

1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1990 37th IEEE International Conference on Solid-State Circuits

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1979 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1975 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1974 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1973 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1972 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1971 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1970 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1969 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1968 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1967 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1966 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1965 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1964 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1962 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1961 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1960 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1959 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1958 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1957 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1956 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1955 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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