NDLI: Power-optimal encoding for DRAM address bus

Please wait, while we are loading the content...

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

International Symposium on Low Power Electronics and Design (ISLPED)

IEEE/ACM International Symposium on Low Power Electronics and Design

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED)

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.

Proceedings of the International Symposium on Low Power Electronics and Design

ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581)

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)

Low-power micromachined microsystems

Design issues for Dynamic Voltage Scaling

Dual-V/sub T/ SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 /spl mu/m technology generation

An adaptive on-chip voltage regulation technique for low-power applications

Robust ultra-low power sub-threshold DTMOS logic

Algorithmic transforms for efficient energy scalable computation

Operating-system directed power reduction

Energy minimization with guaranteed quality of service

Energy efficient design of portable wireless systems

Power consumption reduction in high-speed /spl Sigma//spl Delta/ bandpass modulators

Low power mixed analog-digital signal processing

A low-power Clock and Data Recovery circuit for 2.5 Gb/s SDH receivers

A micro-power mixed signal IC for battery-operated burglar alarm systems

A recursive algorithm for low-power memory partitioning

Optimization of high-performance superscalar architectures for energy efficiency

Gated-V/sub dd/: a circuit technique to reduce leakage in deep-submicron cache memories

Voltage scheduling in the IpARM microprocessor system

MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments

Noise-aware power optimization for on-chip interconnect

New clock-gating techniques for low-power flip-flops

An improved pass transistor synthesis method for low power, high speed CMOS circuits

Achieving utility arbitrarily close to the optimal with limited energy

Power minimization of functional units by partially guarded computation

Systematic cycle budget versus system power trade-off: a new perspective on system exploration of real-time data-dominated applications

Low power sequential circuit design using priority encoding and clock gating

Low-power considerations in the design of Bluetooth

High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies

A three-port nRERL register file for ultra-low-energy applications

Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion

Practical considerations of clock-powered logic

Model and analysis for combined package and on-chip power grid simulation

Cycle-accurate energy consumption measurement and analysis: Case study of ARM7TDMI

Speeding up power estimation of embedded software

High-level power estimation with interconnect effects

"Cool low power" 1 GHz multi-port register file and dynamic latch in 1.8 V, 0.25 /spl mu/m SOI and bulk technology

Low-power digital filtering using multiple voltage distribution and adaptive voltage scaling

Low power self-timed radix-2 division

A rate selection algorithm for quantized undithered dynamic supply voltage scaling

Low-power sensing and digitization of cardiac signals based on sigma-delta conversion

A 1.5 V low-power third order continuous-time lowpass /spl Sigma//spl Delta/ A/D converter

Design of a low-power CMOS baseband circuit for wideband CDMA testbed

A low-voltage CMOS multiplier for RF applications

Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage

Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors

Low power synthesis of sum-of-products computation

A spatially-adaptive bus interface for low-switching communication

A low power unified cache architecture providing power and performance flexibility

Memory system energy: Influence of hardware-software optimizations

Energy-efficient code generation for DSP56000 family

Power-optimal encoding for DRAM address bus

Profile-driven code execution for low power dissipation

An asynchronous matrix-vector multiplier for discrete cosine transform

Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels

Energy-efficient 32/spl times/32-bit multiplier in tunable near-zero threshold CMOS

Tradeoffs and design of an ultra low power UHF transceiver integrated in a standard digital CMOS process

An 8 mA, 3.8 dB NF, 40 dB gain CMOS front-end for GPS applications

Bias boosting technique for a 1.9 GHz class AB RF amplifier

Analysis and design of low-phase-noise ring oscillators

Reliable low-power design in the presence of deep submicron noise

Low power DSP's for wireless communications

Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477)

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379)

Proceedings of 1997 International Symposium on Low Power Electronics and Design

Proceedings of 1996 International Symposium on Low Power Electronics and Design

Power-optimal encoding for DRAM address bus

Content Provider	IEEE Xplore Digital Library
Author	Wei-Chung Cheng Pedram, M.
Copyright Year	2000
Description	Author affiliation: Univ. of Southern California, Los Angeles, CA, USA (Wei-Chung Cheng)
Abstract	This paper presents Pyramid code, an optimal code for transmitting sequential addresses over a DRAM bus. Constructed by finding an Eulerian cycle on a complete graph, this code is optimal for conventional DRAM in the sense that it minimizes the switching activity on the time-multiplexed address bus from CPU to DRAM. Experimental results on a large number of testbenches with different characteristics (i.e. sequential vs. random memory access behaviors) are reported and demonstrate a reduction of bus activity by as much as 50%.
Starting Page	250
Ending Page	252
File Size	357225
Page Count	3
File Format	PDF
ISBN	1581131909
DOI	10.1109/LPE.2000.155293
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-07-26
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Encoding Random access memory Power system reliability Quality of service Energy management Power system management Reflective binary codes Hamming distance Permission Sequential analysis
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: ndl-support@iitkgp.ac.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in