NDLI: Design of a low-power CMOS baseband circuit for wideband CDMA testbed

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Design of a low-power CMOS baseband circuit for wideband CDMA testbed

Content Provider	IEEE Xplore Digital Library
Author	Chunlei Shi Yue Wu Ismail, M.
Copyright Year	2000
Description	Author affiliation: Analog VLSI Lab., Ohio State Univ., Columbus, OH, USA (Chunlei Shi)
Abstract	In this paper, the design and performance of a CMOS base-band circuit for WCDMA direct conversion receiver are presented. Consisting of one 5th-order anti-aliasing filter, one 4th-order tunable channel filter, and three variable gain amplifier (VGA) stages, the baseband chain provides 72 dB gain range with 2 dB gain step and is tunable to select three different bandwidths (from 5 MHz to 20 MHz radio-frequency spacing). It dissipates only 18 mW from a single 3V supply. The input IP3 is 10 dBm, and the input-referred noise in the passband is 41nV//spl radic/(Hz).
Starting Page	222
Ending Page	224
File Size	292843
Page Count	3
File Format	PDF
ISBN	1581131909
DOI	10.1109/LPE.2000.155284
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-07-26
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Circuit testing Baseband Wideband Multiaccess communication Gain Filters Tunable circuits and devices Broadband amplifiers Radiofrequency amplifiers Bandwidth
Content Type	Text
Resource Type	Article

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