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Content Provider | IEEE Xplore Digital Library |
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Author | Jafarzade, S. Jannesari, A. |
Copyright Year | 2013 |
Description | Author affiliation: Tarbiat Modares Univ., Tehran, Iran (Jafarzade, S.; Jannesari, A.) |
Abstract | A Digitally Controlled Oscillator (DCO) for the frequency band of 1700-1900 MHz is presented. This architecture achieves a frequency resolution less than 1-kHz. The DCO is a part of an All-Digital Phase-Locked Loop (ADPLL) for GSM-1800 and GSM-900 applications implemented in a 0.18 μm CMOS process. In this architecture an 18-bit delta sigma digital to analog converter and a voltage controlled LC oscillator is used. The used ΔΣ DAC is a fourth order structure with 450 MHz sampling frequency, Over Sampling Ratio (OSR) =128 and 118 dB SNR. The bandwidth of this ΔΣ DAC is about 1.8 MHz. The phase noise of the presented DCO at 500 kHz offset frequency is -115 dBc/Hz. |
Starting Page | 1 |
Ending Page | 4 |
File Size | 275499 |
Page Count | 4 |
File Format | |
ISBN | 9781467356343 |
DOI | 10.1109/IranianCEE.2013.6599744 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2013-05-14 |
Publisher Place | Iran |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Phase noise CMOS DCO ΔΣ DAC Voltage-controlled oscillators LC oscillator ADPLL Solid state circuits Phase locked loops Tuning |
Content Type | Text |
Resource Type | Article |
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