NDLI: A 32kb 90nm 10T-cell sub-threshold SRAM with improved read and write SNM

Content Provider	IEEE Xplore Digital Library
Author	Hassanzadeh, S. Zamani, M. Hajsadeghi, K.
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran (Hassanzadeh, S.; Zamani, M.; Hajsadeghi, K.)
Abstract	The constraints of power saving have compelled SRAM designers to consider sub-threshold area as a viable choice. The biggest barrier of this progress is the stability of SRAM's cells and the correct operations. In this paper a 10T cell structure has been proposed with 90% read and 50% write SNM improvement in comparison to the conventional 6T cell. The hold SNM value is about the 6T cell SRAM. Also using differential read method in the proposed structure causes high read performance and using simpler sense amplifier. The symmetric configuration of this structure helps the SRAM has simpler layout and lower transistor mismatch. Using 90nm TSMC CMOS, 32kb 10T cell SRAM in sub-threshold area is simulated that confirms the proposed structure performance.
Starting Page	1
Ending Page	5
File Size	1055776
Page Count	5
File Format	PDF
ISBN	9781467356343
DOI	10.1109/IranianCEE.2013.6599737
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-05-14
Publisher Place	Iran
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Layout SRAM cells Stability analysis Circuit stability CMOS integrated circuits Transistors
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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