NDLI: A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction

Content Provider	IEEE Xplore Digital Library
Author	Kwangsoo Han Kahng, A.B. Jongpil Lee Jiajia Li Nath, S.
Copyright Year	2015
Description	Author affiliation: ECE Dept., UC San Diego, San Diego, CA, USA (Kwangsoo Han; Jiajia Li) \|\| CSE Dept., UC San Diego, San Diego, CA, USA (Kahng, A.B.; Nath, S.) \|\| Samsung Electron. Co. Ltd., Hwaseong, South Korea (Jongpil Lee)
Abstract	As combinations of signoff corners grow in modern SoCs, minimization of clock skew variation across corners is important. Large skew variation can cause difficulties in multi-corner timing closure because fixing violations at one corner can lead to violations at other corners. Such “ping-pong” effects lead to significant power and area overheads and time to signoff. We propose a novel framework encompassing both global and local clock network optimizations to minimize the sum of skew variations across different PVT corners between all sequentially adjacent sink pairs. The global optimization uses linear programming to guide buffer insertion, buffer removal and routing detours. The local optimization is based on machine learning-based predictors of latency change; these are used for iterative optimization with tree surgery, buffer sizing and buffer displacement operators. Our optimization achieves up to 22% total skew variation reduction across multiple testcases implemented in foundry 28nm technology, as compared to a best-practices CTS solution using a leading commercial tool.
Starting Page	1
Ending Page	6
File Size	927729
Page Count	6
File Format	PDF
ISBN	9781479980529
DOI	10.1145/2744769.2744776
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Clocks Delays Optimization Inverters Logic gates Routing Algorithms Design
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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