NDLI: Useful clock skew optimization under a multi-corner multi-mode design framework

Content Provider	IEEE Xplore Digital Library
Author	Weixiang Shen Yici Cai Wei Chen Yongqiang Lu Qiang Zhou Jiang Hu
Copyright Year	2010
Description	Author affiliation: EDA Lab, Dept. of Computer Science and Technology, Tsinghua University, Beijing, 100084, China (Weixiang Shen; Yici Cai; Yongqiang Lu; Qiang Zhou) \|\| Magma Design Automation Inc., 1650 Technology Drive, San Jose, CA 95110, U.S.A (Wei Chen) \|\| Dept. of Electrical and Computer Engineering, Texas A&M University, College Station, 77843-3228, U.S.A (Jiang Hu)
Abstract	As VLSI technology scales into sub-65nm realm, the complexity of timing optimization is drastically increased by the consideration of power and variations. Even though designers make great efforts during physical design, they are often faced with still heavy timing violations in deep post-routing stages. For the entire design convergence and timing closure, especially under current multi-corner multi-mode design, some more efficient methods need to be invented. In this work, we propose to address such a kind of issue by exploiting useful clock skew, which can help reduce timing violations rapidly. We also add mode/corner metric balancing measurements to make this method more flexible and applicable especially in such deep stages while the CTS is ready. The results indicate that our method can achieve an average improvements of 33.16% on the worst slack (WS) and 75.56% on the total negative slack (TNS), respectively.
Starting Page	62
Ending Page	68
File Size	3838294
Page Count	7
File Format	PDF
ISBN	9781424464548
ISSN	19483295
e-ISBN	9781424464562
DOI	10.1109/ISQED.2010.5450402
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-03-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Design optimization Timing Routing Process design Electronic design automation and methodology Computer science Design automation Drives Power engineering computing multi-corner multimode Useful clock skew
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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