NDLI: A synthesis methodology aimed at improving the quality of TSC devices

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A synthesis methodology aimed at improving the quality of TSC devices

Content Provider	IEEE Xplore Digital Library
Author	Bolchini, C. Pomante, L. Salice, F. Sciuto, D.
Copyright Year	1999
Description	Author affiliation: Dip. di Elettronica e Inf., Politecnico di Milano, Italy (Bolchini, C.)
Abstract	This paper proposes a synthesis methodology aimed at improving the concurrent error property of combinational TSC devices. The methodology is based on an iterative application of a structural modification of the device (observability modification) and an evaluation of the impact of such a modification. The quality evaluation is performed by means of a cost function for totally self-checking combinational devices which takes into account different aspects besides the area overhead criterion for comparing different realization strategies. The methodology has been validated on a set of MCNC91 benchmarks.
Starting Page	247
Ending Page	255
File Size	265429
Page Count	9
File Format	PDF
ISBN	076950325X
DOI	10.1109/DFTVS.1999.802891
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-11-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Circuit testing Electrical fault detection Fault detection Decision support systems Minimization Encoding Circuit synthesis Built-in self-test VHF circuits
Content Type	Text
Resource Type	Article

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