NDLI: Parity bit code: achieving a complete fault coverage in the design of TSC combinational networks

Content Provider	IEEE Xplore Digital Library
Author	Bolchini, C. Salice, F. Sciuto, D.
Copyright Year	1997
Description	Author affiliation: Dipt. di Sci. dell'Inf., Milan Univ., Italy (Bolchini, C.)
Abstract	A new methodology for designing Totally Self-Checking combinational circuits through the encoding of the primary outputs with the parity code is presented. The parity code requires that each fault modifies an odd number of outputs for providing its detection, that is, each fault has to be oddly observable. The proposed methodology for fulfilling such a constraint consists of a post-synthesis modification of fault observability through either the introduction of an auxiliary output for the examined network node or the replication of the investigated node. A cost evaluation function allows us to select the most convenient solution in terms of overhead and the final 100% TSC circuit.
Starting Page	32
Ending Page	37
File Size	703352
Page Count	6
File Format	PDF
ISBN	0818679042
ISSN	10661395
DOI	10.1109/GLSV.1997.580407
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-03-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Intelligent networks Circuit faults Observability Circuit synthesis Combinational circuits Encoding Electrical fault detection Fault detection Circuit testing Built-in self-test
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Parity bit code: achieving a complete fault coverage in the design of TSC combinational networks