NDLI: An application specific processor for a multi-system navigation receiver

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An application specific processor for a multi-system navigation receiver

Content Provider	IEEE Xplore Digital Library
Author	Aardoom, E. Stravers, P.
Copyright Year	1992
Description	Author affiliation: Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands (Aardoom, E.; Stravers, P.)
Abstract	An application-specific processor for use as the central component for both signal processing and general control tasks of a combined GPS/Loran-C/Omega/MIS navigation receiver is described. It is the first implementation of the transport-triggered Move architecture framework. Vector registers are included to enhance signal processing performance, resulting in a single-cycle multiply-accumulate operation, without compromising scalar performance. The projected clock frequency of this implementation is 125 MHz for a 180000-transistor, 1.6- mu m C MOS sea-of-gates chip.<>
Starting Page	128
Ending Page	131
File Size	308688
Page Count	4
File Format	PDF
ISBN	0818631104
DOI	10.1109/ICCD.1992.276192
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-10-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific processors Navigation Finite impulse response filter Signal processing algorithms IIR filters Signal processing Digital filters Filtering Computer architecture Frequency
Content Type	Text
Resource Type	Article

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