NDLI: Dynamic address compression schemes: a performance, energy, and cost study

Content Provider	IEEE Xplore Digital Library
Author	Jiangjiang Liu Sundaresan, K. Mahapatra, N.R.
Copyright Year	2004
Description	Author affiliation: Dept. of Comp. Sci & Eng., State Univ. of New York, Buffalo, NY, USA (Jiangjiang Liu)
Abstract	Dynamic address compression schemes that exploit address locality can help reduce both address bus energy and cost simultaneously with only a small performance penalty. In this work, we investigate two such schemes and determine their optimal parameters that result in the highest area/cost reductions and least performance penalty for various address buses (both on- and off-chip) in current systems. For addresses compressed with these schemes, we study energy reduction of buses in current and future nanometer technology nodes. Our study uses the cycle-accurate simulator for the Alpha 21264 processor called sim-alpha for performance estimation and accurate interconnect models considering inter-wire capacitances for bus energy estimation. Results show that using address compression results in only small performance overheads (less than 1% for compressing a 38-bit bus to 14 bits) and reduce bus energy dissipation by as much as 13% when applied to on-chip buses in current technologies.
Sponsorship	IEEE Comput. Soc. IEEE Circuits and Syst. Soc
Starting Page	458
Ending Page	463
File Size	408143
Page Count	6
File Format	PDF
ISBN	0769522319
ISSN	10636404
DOI	10.1109/ICCD.2004.1347962
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Capacitance Energy dissipation Wires Delay Logic Encoding Data buses Cost function System-on-a-chip
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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