NDLI: Pulse stream current mode CMOS CNN chip

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Pulse stream current mode CMOS CNN chip

Content Provider	IEEE Xplore Digital Library
Author	Paasio, A. Dawidziuk, A. Porra, V.
Copyright Year	1996
Description	Author affiliation: Electron. Circuit Design Lab., Helsinki Univ. of Technol., Espoo, Finland (Paasio, A.)
Abstract	A new idea of analog cellular neural network (CNN) VLSI implementation is described. The main problem in neural networks realization is the size of adjustable connections between neurons in the net. The weight circuits may occupy more than 90% of the single neuron space. The main advantage of current mode pulse stream neurons is small size of the weight circuit. The simplicity of the building blocks used allows one to operate them with relatively high speed. As compared with the other pulse stream circuits, this approach is based on current pulses. Therefore, for both basic neural operations, summation and multiplication are easy to implement, if only the phase is irrelevant.
Starting Page	457
Ending Page	460
File Size	210699
Page Count	4
File Format	PDF
ISBN	078033261X
DOI	10.1109/CNNA.1996.566617
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-06-24
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Cellular neural networks Switches CMOS technology Neurons Pulse circuits Very large scale integration Frequency Voltage Space vector pulse width modulation Pulse generation
Content Type	Text
Resource Type	Article

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