NDLI: A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling

Content Provider	SpringerLink
Author	Castro Márquez, Carlos Iván Romero Tobar, Edgar Leonardo Strum, Marius Chau, Wang Jiang
Copyright Year	2011
Abstract	Modern Integrated Circuit (IC) design is characterized by a strong trend of Intellectual Property (IP) core integration into complex system-on-chip (SOC) architectures. These cores require thorough verification of their functionality to avoid erroneous behavior in the final device. Formal verification methods are capable of detecting any design bug. However, due to state explosion, their use remains limited to small circuits. Alternatively, simulation-based verification can explore hardware descriptions of any size, although the corresponding stimulus generation, as well as functional coverage definition, must be carefully planned to guarantee its efficacy. In general, static input space optimization methodologies have shown better efficiency and results than, for instance, Coverage Directed Verification (CDV) techniques, although they act on different facets of the monitored system and are not exclusive. This work presents a constrained-random simulation-based functional verification methodology where, on the basis of the Parameter Domains (PD) formalism, irrelevant and invalid test case scenarios are removed from the input space. To this purpose, a tool to automatically generate PD-based stimuli sources was developed. Additionally, we have developed a second tool to generate functional coverage models that fit exactly to the PD-based input space. Both the input stimuli and coverage model enhancements, resulted in a notable testbench efficiency increase, if compared to testbenches with traditional stimulation and coverage scenarios: 22% simulation time reduction when generating stimuli with our PD-based stimuli sources (still with a conventional coverage model), and 56% simulation time reduction when combining our stimuli sources with their corresponding, automatically generated, coverage models.
Starting Page	485
Ending Page	503
Page Count	19
File Format	PDF
ISSN	09238174
Journal	Journal of Electronic Testing
Volume Number	27
Issue Number	4
e-ISSN	15730727
Language	English
Publisher	Springer US
Publisher Date	2011-05-03
Publisher Place	Boston
Access Restriction	Subscribed
Subject Keyword	System-on-chip Functional verification Random-constrained simulation Functional coverage Parameter domains Testbench code automation Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Circuits and Systems
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Automatic generation of random stimuli sources based on Parameter Domains for functional verification

Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs

Functional Verification of DMA Controllers

A methodology aimed at better integration of functional verification and RTL design

Defining and Providing Coverage for Assertion-Based Dynamic Verification

On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST

Cohesive Coverage Management: Simulation Meets Formal Methods

Verification Simulation Acceleration Using Code-Perturbation

Functional Verification Coverage Measurement and Analysis

A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling

Similar Documents

Automatic generation of random stimuli sources based on Parameter Domains for functional verification

Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs

Functional Verification of DMA Controllers

A methodology aimed at better integration of functional verification and RTL design

Defining and Providing Coverage for Assertion-Based Dynamic Verification

On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST

Cohesive Coverage Management: Simulation Meets Formal Methods

Verification Simulation Acceleration Using Code-Perturbation

Functional Verification Coverage Measurement and Analysis

A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling