NDLI: Mechanisms of high hole mobility in (100) nanowire pMOSFETs with width of less than 10nm

Content Provider	IEEE Xplore Digital Library
Author	Nomura, H. Suzuki, R. Kutsuki, T. Saraya, T. Hiramoto, T.
Copyright Year	2012
Description	Author affiliation: Institute of Industrial Science, University of Tokyo, 4-6-1, Komaba, Meguro, Tokyo, 153-8505, Japan (Nomura, H.; Suzuki, R.; Kutsuki, T.; Saraya, T.; Hiramoto, T.)
Abstract	The mechanism of high mobility in <110>-directed nanowire pMOSFETs with height of 10nm on (100) SOI substrate is investigated. The 9nm-wide nanowire pFET has higher mobility than the (100) universal mobility at 300K The temperature dependence measurements of hole mobility show that the high mobility in nanowire pFET originates from the effect of (110) side surface of the nanowire. On the other hand, it is shown that the degraded mobility in 4nm-wide nanowire pFET is caused by the increase in surface roughness scattering.
Starting Page	41
Ending Page	44
File Size	270709
Page Count	4
File Format	PDF
ISBN	9781467301916
e-ISBN	9781467301923
e-ISBN	9781467301909
DOI	10.1109/ULIS.2012.6193352
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-06
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	phonon scattering Temperature dependence universal mobility nanowire MOSFET Scattering surface roughness scattering Logic gates Surface roughness Silicon Rough surfaces Electron devices
Content Type	Text
Resource Type	Article

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Mechanisms of high hole mobility in (100) nanowire pMOSFETs with width of less than 10nm