NDLI: A single-chip K-Band CMOS FMCW radar transceiver

Content Provider	IEEE Xplore Digital Library
Author	Gitae Pyo Songcheol Hong
Copyright Year	2015
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea (Gitae Pyo; Songcheol Hong)
Abstract	This paper presents a K-band FMCW radar transceiver IC, which is integrated in 0.13-μm CMOS technology. In the transmitter part, the class-C topology is adopted in the VCO block to achieve good phase noise performance. In the receiver part, the high gain of the LNA sufficiently suppresses the noise of the next stages to achieve a good noise figure in the receiver and the linearity of the receiver was improved by adoption of a gain control block, thereby achieving a wide dynamic range. As a result, a conversion gain of 35.7 dB, a P1dB of -12.7 dBm, and a DSB noise figure of 5.5 dB are achieved in the receiver part. The tuning range of 23.8~24.5 GHz and the phase noise of -103.1 dBc/Hz @ 1MHz offset are achieved in the transmitter part. The transceiver chip consumes 181.5 mW from a 1.5 V power supply. Using this chip, the K-band FMCW radar module is implemented and verified by measurement of the distance of an object.
Starting Page	1
Ending Page	3
File Size	1057722
Page Count	3
File Format	PDF
ISBN	9781467380638
DOI	10.1109/GSMM.2015.7175111
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-25
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase noise Semiconductor device measurement CMOS radar transceiver Voltage-controlled oscillators K-band Radar Transceivers frequency-modulated continuous wave (FMCW) CMOS integrated circuits
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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