NDLI: Access time optimization of SRAM memory with statistical yield constraint

Content Provider	IEEE Xplore Digital Library
Author	Doorn, T. ter Maten, J. Di Bucchianico, A. Beelen, T. Janssen, R.
Copyright Year	2012
Description	Author affiliation: NXP Semiconductors, High Tech Campus 32 and 46, 5656 AE Eindhoven, the Netherlands (Doorn, T.; Beelen, T.; Janssen, R.) \|\| Dept. Mathematics and Computer Science, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven, the Netherlands (ter Maten, J.; Di Bucchianico, A.)
Abstract	A product may fail when design parameters are subject to large deviations. To guarantee yield one likes to determine bounds on the parameter range such that the fail probability Pfail is small. For Static Random Access Memory (SRAM) characteristics like Static Noise Margin and Read Current, obtained from simulation output, are important in the failure criteria. They also have non-Gaussian distributions. With regular Monte Carlo (MC) sampling we can simply determine the fraction of failures when varying parameters. We are interested to efficiently sample for a tiny fail probability Pfail ≤ $10^{−10}.$ For a normal distribution this corresponds with parameter variations up to 6.4 times the standard deviation σ. Importance Sampling (IS) allows to tune Monte Carlo sampling to areas of particular interest while correcting the counting of failure events with a correction factor. To estimate the number of samples needed we apply Large Deviations Theory, first to sharply estimate the amount of samples needed for regular MC, and next for IS. With a suitably chosen distribution IS can be orders more efficient than regular MC to determine the fail probability Pfail. We apply this to determine the fail probabilities the SRAM characteristics Static Noise Margin and Read Current. Next we accurately and efficiently minimize the access time of an SRAM block, consisting of SRAM cells and a (selecting) Sense Amplifier, while guaranteeing a statistical constraint on the yield target.
Starting Page	1
Ending Page	4
File Size	919853
Page Count	4
File Format	PDF
ISBN	9781467306591
e-ISBN	9788021444706
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-04-17
Publisher Place	Czech Republic
Access Restriction	Subscribed
Rights Holder	BRNO UNIV OF TECH
Subject Keyword	Chaos large deviations Monte Carlo methods Noise Random access memory Gaussian distribution Polynomials failure probabilities monte carlo Optimization Importance sampling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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