NDLI: Design and implementation of low power digital phase-locked loop

Content Provider	IEEE Xplore Digital Library
Author	Saber, M. Jitsumatsu, Y. Khan, M.T.A.
Copyright Year	2010
Description	Author affiliation: Dept. of Informatics, Kyushu University, 744 Motooka, Nishi-ku, Fukuoka-shi, 89-0395, Japan (Saber, M.; Jitsumatsu, Y.) \|\| College of Asia Pacific Studies, Ritsumeikan Asia Pacific University, 1-1 Jumonjibaru, Beppu, Oita, 874-8577, Japan (Khan, M.T.A.)
Abstract	This paper proposes a low power architecture for second order digital phase-locked loop (DPLL). High power consumption of DPLL results from using a look-up table (LUT) in implementing the numerically controlled oscillator (NCO). A new design for NCO is presented in which no LUT is used. Proposed architecture implemented using field programmable gate array (FPGA) consumed 15.44 mw at 100 MHz clock frequency which means a more than 25% saving in power consumption compared to traditional NCO. Furthermore, proposed method also saves FPGA resources and works at faster clock frequency.
Starting Page	928
Ending Page	933
File Size	1458922
Page Count	6
File Format	PDF
ISBN	9781424460168
e-ISBN	9781424460175
DOI	10.1109/ISITA.2010.5649551
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-17
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power demand Table lookup Phase locked loops Digital filters Frequency control field programmable gate array (FPGA) Detectors look-up table (LUT) software defined radio (SDR) spurious free dynamic range (SFDR) Digital phase lock loop(DPLL) numerically controlled oscillator (NCO) Clocks
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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