NDLI: On-chip active RF tracking filter with 60dB $3^{rd}-order$ harmonic rejection for digital TV tuners

Please wait, while we are loading the content...

2015 International SoC Design Conference (ISOCC)

2013 International SoC Design Conference (ISOCC)

2012 International SoC Design Conference (ISOCC)

2011 International SoC Design Conference

2010 International SoC Design Conference

2009 International SoC Design Conference (ISOCC)

2008 International SoC Design Conference

Volume 03 - 2008

Volume 02 - 2008

Volume 01 - 2008

A 9-context optically reconfigurable gate array

A Sigma-Delta class D audio power amplifier in 0.35μm CMOS technology

Fast RSSI circuit using novel power detector for wireless communication

An active-RC filter with variable bandwidth and channel-selectivity characteristics

CMOS OTA compensating transconductance linearity with PMOS path

Design trend of energy-efficient CAMs

A multi-mode entropy decoder with a generic table partition strategy

On reducing power consumption and code size of H.264 intra luma prediction on multicore DSP

Performance and wake-up schedule optimization of power gating design

A low power ZigBee baseband processor

A generalized framework for energy savings in real-time multiprocessor systems

Power reduction controll for multicores in OSCAR multigrain parallelizing compiler

Multiprocessor SoC design framework on Tightly-Coupled Thread model

Real-time operating systems for multicore embedded systems

32nm high K metal gate (HKMG) designs for low power applications

DFM optimization of standard cells considering random and systematic defect

Parametric yield-aware sign-off flow in 65/45nm

Reusable platform design methodology for SoC integration and verification

A new high-resolution, temperature-compensated cyclic time-to-digital converter

An accurate analysis of a VCO voltage regulator

Multi functional range finder employing a dual imager core on a single chip

Analysis on light attenuation through multi-metal-layers for CMOS image sensors on system LSIs

Low voltage time based CMOS active pixel sensor

Portfolio of FinFET memories: Innovative techniques for an emerging technology

A low power digital pixel sensor with a dynamically biased ADC

Power grid optimization with consideration of timing violation by IR drop

Stability enhancement techniques for nanoscale SRAM circuits: A comparison

Design ASNoC for low-power SoCs

Behavioral partitioning with exploiting function-level parallelism

On modeling and sensitivity of via count in SOC physical implementation

LTR: A low-overhead and reliable routing algorithm for network on chips

ILP based data parallel multi-task mapping/scheduling technique for MPSoC

Communication modeling for system-level design

Efficient variable length decoding using N-bit code table for multi-format video applications

Multi-codec variable length decoder design with configurable processor

Fast mode decision for h.264 intra prediction with prediction samples easy to generate

Design of high-performance unified motion estimation IP for H.264/MPEG-4 video CODEC

The lifting-based DWT filter hardware design for JPEG2000

A discussion on SRAM circuit design trend in deeper nano-meter era

A new SRAM cell design using CNTFETs

Digital integrated circuit design for system-on-glass

A low power 8T SRAM cell design technique for CNFET

Multicore SoC for embedded systems

Performance evaluation of a reconfigurable instruction set processor

A single cycle accessible two-level cache architecture for reducing the energy consumption of embedded systems

Redundancy techniques for SRAM leakage reduction in presence of within-die delay variation

Efficient construction of minimal Spanning Tree avoiding rectilinear directional obstacles

A heuristic method to reduce fault candidates for a speedy fault diagnosis

PDSDL: A dynamic System Description Language

Variable-length block nine-coded compression technique with Huffman codes and symbol merging

Scan order decision algorithm for improving the reliability of PDP data drivers

System-On-Chip technology-based on-the-fly audio data acquisition, monitoring and displaying system using FPGA

Design of a geometry engine for mobile 3D graphics

Hybrid architecture of full-search block-matching motion estimation circuit for MPEG-4 encoder

Improved frame selector for multi-reference motion estimation

The development of an energy-awared mobile 3D graphics SoC with real-time performance/energy monitoring and control

System anlaysis of power-aware H.264/AVC encoder based on fast inter prediction

Energy-saving techniques for low-power graphics processing unit

Reconfigurable motion estimation architecture design on H.264/AVC for power aware mobile application

TunableVP: A Tunable Virtual Platform for easy SoC design space exploration

Energy-effective design & implementation of an embedded VLIW DSP

Speeding up SoC virtual platform simulation by data-dependency aware virtual synchronization

A new routing algorithm for irregular mesh NoCs

100-Gb/s three-parallel Reed-Solomon based foward error correction architecture for optical communications

High performance NoC architecture for two hidden layers BP Neural Network

New address generation scheme for memory-based FFT processor using multiple radix-2 butterflies

An all-digital phase-locked loop with fast acquisition and low jitter

R-less and C-less self-sampled ASK demodulator for lower ISM band applications

Direction-based routing methodology for irregular NoCs

Processor energy estimation method using cycle-approximate simulator

The proposed on-chip bus system with GALDS topology

Performance evaluation of Butterfly on-Chip Network for MPSoCs

The Kautz mesh: A new topology for SoCs

FPGA based asynchronous pipelined multiplier with intelligent delay controller

Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations

FPGA based asynchronous pipelined viterbi decoder using two phase bundled-data protocol

Fluidic manipulation and self-assembly of microdevices in railed microfluidic channels

Automatic generation of diagrams for system-on-chip architectures

Modeling functional unit delays for bit-level chaining

Scheduling considering bit level delays

A design of full-CMOS VDSL2 receiver in 0.25μm CMOS process

an optimized rendering algorithm for hardware implementation of openVG 2D vector graphics

Multiplier less fast loss less integer DCT for H.264

A 1V 2.8Gbps 0.18μm CMOS inverter-based digital differential transmitter with calibrations of termination and mismatch

High performance clocked CMOS adiabatic inverter driver with single stage data input

Non-invasive direct probing for on-chip voltage measurement

Circuit modeling of Multi-Layer Ceramic Capacitors using s-parameter measurements

Mapping control intensive kernels onto coarse-grained reconfigurable array architecture

The Javelin: A Java accelerator based on hardware translation method

An effective parallel ALPG using instruction unrolling for high speed memory testing

Reducing cost of frequency binning: An effective and efficient approach

Segmented scan architecture using segment grouping for test cost reduction

A new approach for circuit design optimization using Genetic Algorithm

μCRL: A Computer Science based approach for specification and verification of hardware circuits

On-line learning based dynamic thermal management for multicore systems

Automatic mapping of application to coarse-grained reconfigurable architecture based on high-level synthesis techniques

Implementing the component-based software engineering in embedded systems

Millimeter-wave CMOS power amplifiers in common-source MOSFETs

On-chip active RF tracking filter with 60dB $3^{rd}-order$ harmonic rejection for digital TV tuners

Investigation of forward body bias effects on TSPC RF frequency dividers in 0.18 μm CMOS

Highly linear CMOS low noise amplifier with IIP3 boosting technique

Design of optical fiber sensor driving IC for structure monitoring system

A 26mW dual-mode RF receiver for GPS/Galileo with L1/L1F and L5/E5a bands

The dependability analysis of LIN network for adaptive front-lighting system

Area-efficent power clamp circuit using gate-coupled structure for Smart Power ICs

An improved RF MOSFET model including scalable gate resistance and external inductances

A L1-Band RF receiver for GPS aplication in 0.13um CMOS technology

Scalable modeling of spiral inductor in 0.13μm RF CMOS process

On-chip active RF tracking filter with 60dB $3^{rd}-order$ harmonic rejection for digital TV tuners

Content Provider	IEEE Xplore Digital Library
Author	Yang Sun Jeong-seon Lee Sang-gug Lee
Copyright Year	2008
Description	Author affiliation: Eng. Dept., Inf. & Commun. Univ., Daejeon (Yang Sun; Jeong-seon Lee; Sang-gug Lee)
Abstract	A new structure of RF tracking filter to solve the linearity and harmonic mixing problem in DTV (digital TV) tuner is proposed in this paper. The proposed structure composed of two filters: harmonic rejection tracking filter (HRTF) and RF tracking filter (RFTF). They are activated / deactivated by complementary digital control switches. HRTF works in the frequency range 48~287 MHz. It can reject not only 3 rd-order harmonic by more than 60 dB but also unwanted channel signal from 5 to 15 dB. The RFTF can reject unwanted signal from 287~860 MHz. The proposed structure can realize pre-band selection function in the tuner front-end and covers a wide frequency range from 48-860 MHz. The center frequency and the bandwidth of both filters can be tuned by adopting the proposed tuning method. Also, the proposed structure can be implemented without any off-chip component. Simulation results show the tunable ability of the center frequency from 48 to 860 MHz, and the bandwidth from 8~20 MHz. These features are obtained drawing 19.8 mA (7.2 mA from RFTF, 12.6 mA from HRTF) current from a 1.2-V supply in a standard 0.13 um CMOS technology.
File Size	212855
File Format	PDF
ISBN	9781424425983
DOI	10.1109/SOCDC.2008.4815658
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-24
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Tuners bandpass filter harmonic rejection Digital filters Power harmonic filters Radio frequency Digital control Linearity digital TV tuner active RF tracking filter Bandwidth on chip harmonic mixing Active filters CMOS technology Digital TV
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in