NDLI: Parasitic characteristics of BGA packages

Content Provider	IEEE Xplore Digital Library
Author	Chang, T. Cheng, P.H. Huang, H.C. Lee, R.S. Lo, R.
Copyright Year	1998
Description	Author affiliation: Ind. Technol. Res. Inst., Hsinchu, Taiwan (Chang, T.)
Abstract	With the rapid progress in CMOS VLSI technology, feature size has decreased dramatically from 0.5 to 0.25 /spl mu/m, while chip drivers have become faster with sub-ns transitions. Most modern ICs work with a low power supply voltage with a low logic swing, and have widened their data bus from 16 to 32 or even 64 bits. All of these factors push modern packages toward greater pin counts, smaller form factors, and better electrical performance. As packages convey signals between ICs and act as inductance and capacitance components (at certain operating frequencies), packages with lower parasitic effects thus have better electrical performance. For high speed multi-function ICs, ball grid array (BGA) packages have increased their market share and thus have severe parasitic effect requirements. Simulations and measurements of electrical parasitics are crucial studies in the development of BGA packages and package selection for advanced ICs. In this paper, four types of BGA package, including 2-layer PBGA (plastic BGA), TEPBGA (thermally and electrically enhanced PBGA), FCPBGA (flip chip PBGA) and 4-layer PBGA, have been studied. The TEPBGA includes a heat slug as ground plane. All of the BGA packages are based on organic BT substrates. The paper describes: (a) the electrical simulation technique for each package, where realistic signal paths were analyzed and modeled; (b) the measurement method for each package. The results are summarized in terms of capacitance and inductance for each package, and both simulation and measurement data are presented.
Starting Page	124
Ending Page	129
File Size	332398
Page Count	6
File Format	PDF
ISBN	081868433X
DOI	10.1109/IPDI.1998.663644
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-02-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device measurement Low voltage Inductance Power supplies CMOS logic circuits Electric variables measurement Packaging Very large scale integration CMOS technology Parasitic capacitance
Content Type	Text
Resource Type	Article

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