NDLI: Fast Hierarchical Cache Directory: A Scalable Cache Organization for Large-Scale CMP

Content Provider	IEEE Xplore Digital Library
Author	Chongmin Li Haixia Wang Yibo Xue Xi Zhang Dongsheng Wang
Copyright Year	2010
Abstract	As more processing cores are integrated into one chip and the feature size continues to shrink, the increasing on-chip access latency complicates the design of the on-chip last-level cache for chip multiprocessors. At the same time, the overhead of maintaining on-chip directory cannot be ignored as the number of processing cores increasing. There is an urgent need for scalable organization of on-chip last-level cache. In this work, we propose fast hierarchical cache directory for tiled CMP, which divides CMP tiles into multiple regions hierarchically, and combines it with data replication. Multi-level directory is used to record the share information within a region and assist the regional home node to complete operation efficiently. Fast directory is used to get lower L2 slice access latency at the same time. Most cache requests to last-level cache can be handled within the local level-1 region. Evaluation indicates this architecture is highly scalable. Simulation results show that for a 16-core CMP, hierarchical cache directory reduces average access latency to last-level cache by 46.35% and average on-chip network traffic by 19.25% respectively. The system performance is increased by 20.82% at the same time.
Starting Page	367
Ending Page	376
File Size	385408
Page Count	10
File Format	PDF
ISBN	9781424481330
DOI	10.1109/NAS.2010.25
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-15
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Tiles Organizations Coherence Multi-level directory Chip multiprocessors System-on-a-chip Wire Optimization Delay Hierarchical cache directory
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Towards hierarchical cluster based cache coherence for large-scale network-on-chip

Directory-based cache coherence protocol for power-aware chip-multiprocessors

A composite and scalable cache coherence protocol for large scale cmps.

Network caching for Chip Multiprocessors

An adaptive cache coherence protocol for chip multiprocessors

A hybrid NoC design for cache coherence optimization for chip multiprocessors

A survey on cache coherence for tiled many-core processor

Scalable Proximity-Aware Cache Replication in Chip Multiprocessors

Scalable directory organization for tiled cmp architectures (2008)

Fast Hierarchical Cache Directory: A Scalable Cache Organization for Large-Scale CMP

Similar Documents

Towards hierarchical cluster based cache coherence for large-scale network-on-chip

Directory-based cache coherence protocol for power-aware chip-multiprocessors

A composite and scalable cache coherence protocol for large scale cmps.

Network caching for Chip Multiprocessors

An adaptive cache coherence protocol for chip multiprocessors

A hybrid NoC design for cache coherence optimization for chip multiprocessors

A survey on cache coherence for tiled many-core processor

Scalable Proximity-Aware Cache Replication in Chip Multiprocessors

Scalable directory organization for tiled cmp architectures (2008)

Fast Hierarchical Cache Directory: A Scalable Cache Organization for Large-Scale CMP