NDLI: Multiple-parameter side-channel analysis: A non-invasive hardware Trojan detection approach

Content Provider	IEEE Xplore Digital Library
Author	Narasimhan, S. Dongdong Du Chakraborty, R.S. Paul, S. Wolff, F. Papachristou, C. Roy, K. Bhunia, S.
Copyright Year	2010
Description	Author affiliation: Purdue University, West Lafayette, Indiana, USA (Roy, K.) \|\| Case Western Reserve University, Cleveland, Ohio, USA (Narasimhan, S.; Dongdong Du; Chakraborty, R.S.; Paul, S.; Wolff, F.; Papachristou, C.; Bhunia, S.)
Abstract	Malicious alterations of integrated circuits during fabrication in untrusted foundries pose major concern in terms of their reliable and trusted field operation. It is extremely difficult to discover such alterations, also referred to as “hardware Trojans” using conventional structural or functional testing strategies. In this paper, we propose a novel non-invasive, multiple-parameter side-channel analysis based Trojan detection approach that is capable of detecting malicious hardware modifications in the presence of large process variation induced noise. We exploit the intrinsic relationship between dynamic current (IDDT ) and maximum operating frequency (Fmax) of a circuit to distinguish the effect of a Trojan from process induced fluctuations in IDDT . We propose a vector generation approach for IDDT measurement that can improve the Trojan detection sensitivity for arbitrary Trojan instances. Simulation results with two large circuits, a 32-bit integer execution unit (IEU) and a 128-bit Advanced Encryption System (AES) cipher, show a detection resolution of 0.04% can be achieved in presence of ±20% parameter (Vth) variations. The approach is also validated with experimental results using 120nm FPGA (Xilinx Virtex-II) chips.
Starting Page	13
Ending Page	18
File Size	988947
Page Count	6
File Format	PDF
ISBN	9781424478118
e-ISBN	9781424478125
DOI	10.1109/HST.2010.5513122
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fluctuations Circuit simulation Integrated circuit reliability Circuit testing Fabrication Hardware Trojan Frequency Hardware Foundries Circuit noise Cryptography Multiple-parameter test Side channel analysis
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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