NDLI: A 3.4-mW 2.4-GHz frequency synthesizer in 0.18 µm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Carmo, J.P. Mendes, P.M. Couto, C. Correia, J.H.
Copyright Year	2009
Description	Author affiliation: University of Minho, Dept. Industrial Electronics, Campus Azurem, 4800-058 Guimaraes, PORTUGAL (Carmo, J.P.; Mendes, P.M.; Couto, C.; Correia, J.H.)
Abstract	This paper presents a low-power/low-voltage frequency synthesizer for the frequency of 2.4 GHz, which were designed and fabricated in a standard 0.18 µm CMOS process. This synthesizer is based on a Phase-locked Loop (PLL) with a integer divider in the feedback loop and for a voltage supply of only 1.8 V, it presents a total power consumption of 3.4 mW. The power consumptions for the Voltage-controlled oscillator, phase-frequency difference/charge-pump and for the divider are 2 mW, 1 mW, 420 µW, respectively. The PLL is very fast, e.g., it takes only 1.6 µs to lock, which makes it a perfect companion for devices where frequency hops must be done very quickly.
Starting Page	266
Ending Page	269
File Size	647940
Page Count	4
File Format	PDF
ISBN	9781424443208
DOI	10.1109/DTIS.2009.4938068
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-06
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency synthesizers Energy consumption Charge pumps Phase frequency detector Circuits Frequency conversion CMOS process Phase locked loops Feedback loop PLL CMOS Voltage-controlled oscillators wireless microsystems
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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