NDLI: Decimal division: Algorithms and FPGA implementations

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2014 IX Southern Conference on Programmable Logic (SPL)

2012 VIII Southern Conference on Programmable Logic

2011 VII Southern Conference on Programmable Logic (SPL)

2010 VI Southern Programmable Logic Conference (SPL)

Table of contents

Reconfigurable Computing: boosting software education for the multicore era: Why we need to reinvent computing

Session 1 - embedded processors and IP cores

The supersmall soft processor

Libor market model simulation on an FPGA parallel machine

Protection of microprocessor-based cores for FPL devices

FPGA-based smart sensor implementation with precise frequency to digital converter for flow measurement

Session 2 - system-on-chip

A Genetic Programming based approach for efficiently exploring architectural communication design space of MPSoCs

An environment for energy consumption analysis of cache memories in SoC platforms

The development of a hardware abstraction layer generator for system-on-chip functional verification

A placement tool for a NOC-based dynamically reconfigurable system

Session 3 - computer arithmetic

FPGA based floating-point library for CORDIC algorithms

Montgomery modular multiplication on reconfigurable hardware: Fully systolic array vs parallel implementation

Decimal division: Algorithms and FPGA implementations

Parallel decimal multipliers using binary multipliers

Session 4 - image processing and vision

A high performance hardware architecture for the H.264/AVC half-pixel interpolation unit

FPGA-based real time processing of the plenoptic wavefront sensor for the european solar telescope (EST)

Architecture for binary mathematical morphology reconfigurable by genetic programming

An optimized label-broadcast parallel algorithm for connected components labeling

Session 5.1 - FPGA architectures for specific applications

A general-purpose dynamically reconfigurable SVM

FPGA hierarchical architecture for a Positron Emission Tomography Scanner

An FPGA based architecture for complex rule matching with stateful inspection of multiple TCP connections

Session 5.2 - fault tolerance, test & verification

Delay modeling for power noise-aware design in Spartan-3A FPGAs

Ring oscillators as thermal sensors in FPGAs: Experiments in low voltage

Design and implementation of packet switching capabilities on 10GbE MAC core

Multiprotocol transceiving, Formatting and Temperature monitoring FPGA based unit

Motion detection of vehicles based on FPGA

A reconfigurable general framework for pipelined image processing: A color mathematical morphology application

A full duplex implementation of Internet Protocol version 4 in an FPGA device

Using an FPGA digital clock manager to generate sub-nanosecond phase shifts for lidar applications

Implementation of Split-Radix Fast Fourier Transform on FPGA

Efficiency evaluation and architecture design of SSD unities for the H.264/AVC standard

A flexible implementation of a matrix Laurent series-based 16-point fast Fourier and Hartley transforms

Implementation of a SigmaBoost-based ensemble of SVM in a multiple processor system on chip

Hardware design for fast intermode decision and for residues generaton in a variable block size motion estimation compliant with the H.264/AVC video coding standard

Rec-Bench: A tool to create benchmark for reconfigurable computers

Research and Partial analysis of overhead of a partition model for a Partially Reconfigurable hardware in a data-driven machine - chicflow

Acceleration of HMM-based speech recognition system by parallel FPGA Gaussian calculation

2009 5th Southern Conference on Programmable Logic (SPL)

2008 4th Southern Conference on Programmable Logic

2007 3rd Southern Conference on Programmable Logic

Decimal division: Algorithms and FPGA implementations

Content Provider	IEEE Xplore Digital Library
Author	Deschamps, J.-P. Sutter, G.
Copyright Year	2010
Description	Author affiliation: University Rovira i Virgili, Tarragona, Spain (Deschamps, J.-P.) \|\| Universidad Autonoma de Madrid, Spain (Sutter, G.)
Abstract	The work reported in this paper is devoted to the FPGA implementation of decimal dividers. Two types of dividers are described. The first one implements a decimal non-restoring like algorithm and uses ripple-carry operators. For medium size operators it gives a good compromise between cost and latency. The second one implements an SRT-like algorithm and uses carry-free operators. Their latencies are close to that of a binary radix-16 divider with the same range, implemented in the same FPGA.
Starting Page	67
Ending Page	72
File Size	686304
Page Count	6
File Format	PDF
ISBN	9781424463091
e-ISBN	9781424463114
DOI	10.1109/SPL.2010.5483000
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-03-24
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Hardware Field programmable gate arrays Delay Arithmetic
Content Type	Text
Resource Type	Article

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