NDLI: A 4-Mbit Non-Volatile Chalcogenide-Random Access Memory Designed for Space Applications

Content Provider	IEEE Xplore Digital Library
Author	Bin Li Bumgarner, A. Pirkl, D. Stobie, J. Neiderer, W. Graziano, M. Burcin, L. Storey, T. Orlowsky, B. Hunt, K.K. Rodgers, J. Maimon, J.
Copyright Year	2006
Description	Author affiliation: BAE Syst., Manassas, VA (Bin Li; Bumgarner, A.; Pirkl, D.; Stobie, J.; Neiderer, W.; Graziano, M.; Burcin, L.; Storey, T.; Orlowsky, B.)
Abstract	A 4 Mbit non-volatile chalcogenide-random access memory $(C-RAM^{TM})$ has been designed and fabricated in RH 25, a radiation hardened CMOS technology. The top-down design focused on accommodating chalcogenide process variations and satisfying space system specifications. The optimized band-gap circuit supplies reference current and voltage that meet temperature and voltage requirements. The innovative write circuitry supplies appropriate currents (amplitude and shape) to the chalcogenide memory cells to allow them to be programmed either in amorphous state (write "0") or crystalline state (write "1"). The on-chip pulse generator circuit can provide multiple pulse widths for write "0" and write "1". The write circuits have a dedicated power supply, which can be removed to place the part in a read only mode. The read circuitry includes a voltage limiting circuit, an adjustable current reference, an adjustable pre-charge circuit, and a sense amplifier to accurately sense the current difference between cells programmed as "0" or "1". A localized, redundant cell architecture is implemented with shared read/write circuits to improve yield without impacting access times. The redundant cells can be tested prior to laser fusing or used to monitor endurance. Considerations for testability such as direct chalcogenide cell access, margin testing, analog monitors, and endurance acceleration have been implemented. Noise and power reduction techniques have also been used globally.
Starting Page	64
Ending Page	70
File Size	5169956
Page Count	7
File Format	PDF
ISBN	078039738X
DOI	10.1109/NVMT.2006.378879
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Radiation hardening Photonic band gap memory Pulse amplifiers Current supplies Circuit testing Chalcogenide phase change nonvolatile Nonvolatile memory Space technology Voltage CMOS technology Monitoring
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 4-Mbit Non-Volatile Chalcogenide Random Access Memory

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