NDLI: ElastiNoC: A self-testable distributed VC-based Network-on-Chip architecture

Content Provider	IEEE Xplore Digital Library
Author	Seitanidis, I. Psarras, A. Kalligeros, E. Nicopoulos, C. Dimitrakopoulos, G.
Copyright Year	2014
Description	Author affiliation: Electr. & Comput. Eng., Univ. of Cyprus, Nicosia, Cyprus (Nicopoulos, C.) \|\| Electr. & Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece (Seitanidis, I.; Psarras, A.; Dimitrakopoulos, G.) \|\| Inf. & Commun. Syst. Eng., Univ. of the Aegean, Samos, Greece (Kalligeros, E.)
Abstract	Network-on-Chip (NoC) design tries to keep a balance between network performance and physical implementation flexibility. The adoption of Virtual Channels (VC) holds promise for scalable NoC design. VCs allow for traffic separation and isolation, enable deadlock avoidance and improve network performance. In this paper, we present ElastiNoC, a novel distributed VC-based router architecture that enjoys all the benefits offered by VCs and leads to efficient silicon-aware implementations. The proposed architecture utilizes an efficient buffering strategy and allows for modular pipelined organizations that increase the clock frequency. Moreover, it offers maximum freedom in terms of physical placement, by allowing the NoC components to be physically spread throughout the chip, irrespective of the network topology. The combined effect of all supported features enables significant delay reductions under equal performance, when compared to state-of-the-art VC-based NoC implementations. Moreover, the careful addition of self-test structures allows ElastiNoC to enjoy fully distributed Built-In Self Testability (BIST), where testing unfolds in phases and reaches high fault coverage with small test application time.
Starting Page	135
Ending Page	142
File Size	815083
Page Count	8
File Format	PDF
ISBN	9781479953479
DOI	10.1109/NOCS.2014.7008772
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-17
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Ports (Computers) Routing Delays Registers Resource management Pipeline processing Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

ElastiNoC: A Self-Testable Distributed VC-based Network-on-Chip Architecture

Timing-resilient Network-on-Chip architectures

Variable-width datapath for on-chip network static power reduction

Design and analysis of five port router for network on chip

A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems

A spare link based reliable Network-on-Chip design

Pipelined NoC router architecture design with buffer configuration exploration on FPGA

A speculative arbiter design to enable high-frequency many-VC router in NoCs

An architecture based routing for heterogeneous fat tree network on chip

ElastiNoC: A self-testable distributed VC-based Network-on-Chip architecture

Similar Documents

ElastiNoC: A Self-Testable Distributed VC-based Network-on-Chip Architecture

Timing-resilient Network-on-Chip architectures

Variable-width datapath for on-chip network static power reduction

Design and analysis of five port router for network on chip

A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems

A spare link based reliable Network-on-Chip design

Pipelined NoC router architecture design with buffer configuration exploration on FPGA

A speculative arbiter design to enable high-frequency many-VC router in NoCs

An architecture based routing for heterogeneous fat tree network on chip

ElastiNoC: A self-testable distributed VC-based Network-on-Chip architecture