NDLI: Increasing NoC power estimation accuracy through a rate-based model

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2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS)

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)

2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip

Proceedings of the Fifth ACM/IEEE International Symposium

2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

2009 3rd ACM/IEEE International Symposium on Networks-on-Chip

3rd ACM/IEEE international symposium on networks-on-chip

3rd ACM/IEEE international symposium on networks-on-chip

Organizing committee

Program committee

Steering committee

Additional reviewers

Message from the chairs

Table of contents

Keynote 1 NoCs: It is about the memory and the programming model

HiRA: A methodology for deadlock free routing in hierarchical networks on chip

Using adaptive routing to compensate for performance heterogeneity

Fault-tolerant architecture and deflection routing for degradable NoC switches

Adaptive stochastic routing in fault-tolerant on-chip networks

Static virtual channel allocation in oblivious routing

Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip

Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links

Recursive partitioning multicast: A bandwidth-efficient routing for Networks-on-Chip

Analytical modeling and evaluation of On-Chip Interconnects using Network Calculus

Energy efficient application mapping to NoC processing elements operating at multiple voltage levels

The design of a latency constrained, power optimized NoC for a 4G SoC

Performance Evaluation of NoC Architectures for Parallel Workloads

Packet-level static timing analysis for NoCs

Increasing NoC power estimation accuracy through a rate-based model

On-Chip photonic interconnects for scalable multi-core architectures

A Modeling and exploration framework for interconnect network design in the nanometer era

Power reduction through physical placement of asynchronous routers

Networks-on-chip in emerging interconnect paradigms: Advantages and challenges

Keynote 2 NoC's at the center of chip architecture: Urgent needs (today) and what they must become (future)

Analysis of photonic networks for a chip multiprocessor using scientific applications

Scalability of network-on-chip communication architecture for 3-D meshes

Silicon-photonic clos networks for global on-chip communication

Contention-free on-chip routing of optical packets

Connection-centric network for spiking neural networks

A Communication and configuration controller for NoC based reconfigurable data flow architecture

Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions

Best of both worlds: A bus enhanced NoC (BENoC)

Flow-aware allocation for on-chip networks

CTC: An end-to-end flow control protocol for multi-core systems-on-chip

Performance and power efficient on-chip communication using adaptive virtual point-to-point connections

Keynote 3 (Banquet Talk) Digital space

A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network

A modular synchronizing FIFO for NoCs

Estimating reliability and throughput of source-synchronous wave-pipelined interconnect

Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture

Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers

Diagnosis of interconnect shorts in mesh NoCs

BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel

Exploring concentration and channel slicing in on-chip network router

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)

First International Symposium on Networks-on-Chip (NOCS'07)

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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