NDLI: Equivalence checking of nonlinear analog circuits for hierarchical AMS System Verification

Content Provider	IEEE Xplore Digital Library
Author	Steinhorst, S. Hedrich, L.
Copyright Year	2012
Description	Author affiliation: TUM CREATE, Singapore (Steinhorst, S.) \|\| University of Frankfurt/Main, Germany (Hedrich, L.)
Abstract	In this contribution a novel formal methodology for equivalence checking of analog circuits is proposed. In order to prove the behavioral equivalence of two circuit implementations such as a transistor netlist and a corresponding behavioral model, guaranteed coverage of the complete reachable state space for each of the two circuits under verification is obtained by an efficient input stimuli generation algorithm. These input stimuli are processed by a conventional circuit simulator to obtain simulation results covering each system's complete dynamic behavior. By automatically comparing the simulation results using specific error measures, the level of equivalence of both systems is determined. Simulation by complete state space-covering input stimuli guarantees the equivalence checking results to be sound for every possible state and input stimulus of the circuits under verification, which allows safe application of analog behavioral models in hierarchical AMS system simulation flows. The application to example circuits shows the feasibility of the approach.
Starting Page	135
Ending Page	140
File Size	751110
Page Count	6
File Format	PDF
ISBN	9781467326575
e-ISBN	9781467326582
e-ISBN	9781467326568
DOI	10.1109/VLSI-SoC.2012.6379019
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Runtime Heuristic algorithms Measurement uncertainty Analog circuits Transistors Integrated circuit modeling Transient analysis
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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