NDLI: Research on VHDL RTL synthesis system

Content Provider	IEEE Xplore Digital Library
Author	Haifeng Zhou Zhenghui Lin Wei Cao
Copyright Year	2002
Description	Author affiliation: VLSI Res. Inst., Shanghai Jiao Tong Univ., China (Haifeng Zhou)
Abstract	In this paper, we present a prototype of VHDL RTL synthesis system- VHB. This prototype can be divided into three, parts. The first part is a VHDL synthesis subset parser, the second part is an optimizer at language level, and the third part is an inferencer responsible for getting the netlist. The parser checks whether the input VHDL descriptions are in accordance with the grammar of synthesis subset, and generates the parsing tree of input descriptions. The parsing tree generated by the parser is provided to the a second part of the prototype to perform language level optimization, which includes redundant and ambiguous elimination in assignment statements; expression optimization; common sub-expression extraction; operator reordering; resource sharing and loop unrolling. The task of the third part is very simple, which generates the netlist.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech, Council (TTTC)
Starting Page	99
Ending Page	103
File Size	236969
Page Count	5
File Format	PDF
ISBN	0769514537
DOI	10.1109/DELTA.2002.994596
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-01-29
Publisher Place	New Zealand
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit synthesis Computer languages Electronic design automation and methodology Delay effects Prototypes Very large scale integration Very high speed integrated circuits Circuit synthesis Resource management Hardware design languages
Content Type	Text
Resource Type	Article

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