NDLI: Periodic real-time scheduling for FPGA computers

Content Provider	IEEE Xplore Digital Library
Author	Danne, K. Platzner, M.
Copyright Year	2005
Description	Author affiliation: Design of Parallel Syst. Group, Paderborn Univ., Germany (Danne, K.)
Abstract	Todays reconfigurable hardware devices, such as FPGAs, have high densities and allow for the execution of several hardware tasks in parallel. This paper deals with scheduling periodic real-time tasks to such an architecture, a problem which has not been considered before. We formalize the real-time scheduling problem and propose two preemptive scheduling algorithms. The first is an adaption of the well-known earliest deadline first (EDF) technique to the FPGA execution model. The algorithm reveals good scheduling performance; task sets with system utilizations of up to 85% can be feasibly scheduled. However, the EDF approach is practical only for a small number of tasks, since there is no efficient schedulability test. The second algorithm uses the concept of servers that reserve area and execution time for other tasks. Tasks are successively merged into servers, which are then scheduled sequentially. While this method can only feasibly schedule task sets with a system utilization of up to some 50%, it is applicable to large tasks sets as the schedulability test runs in polynomial time. Equally important, the method requires only a small number of FPGA configurations which directly translates into reduced memory requirements.
Starting Page	117
Ending Page	127
File Size	340185
Page Count	11
File Format	PDF
ISBN	3902463031
DOI	10.1109/WISES.2005.1438720
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-20
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	HAMBURG UNIV OF TECH
Subject Keyword	Concurrent computing Computer science Design engineering Processor scheduling Computer architecture Hardware Silicon Field programmable gate arrays Scheduling algorithm Testing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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