NDLI: Lower power, lower delay design scheme for CMOS tapered buffers

Content Provider	IEEE Xplore Digital Library
Author	Shebaita, A. Ismail, Y.
Copyright Year	2009
Description	Author affiliation: IBM (Shebaita, A.) \|\| Nanoelectronics integrated systems Northwestern University/Nile University (Ismail, Y.)
Abstract	This paper proposes lower power, lower delay design for CMOS tapered buffers. A slight increase in the threshold voltage is shown to have an exponential effect in reducing the total power dissipation. The corresponding increase in the propagation delay is compensated for by increasing the number of buffer stages such that there is still an overall significant reduction in the total power dissipation. As compared to the constant threshold voltage design based on a cost function of $PT^{2},$ the proposed scheme can lead to either a power dissipation reduction of about 70% while maintaining the same delay, or up to 30% in power dissipation with 10% propagation delay reduction, respectively, in 65 nm technology with VDD=1V, minimum size gate capacitance, Cg=1.5fF, and minimum size output capacitance, C0=1fF. Closed form expressions that give the optimum threshold voltage and number of stages are presented.
Starting Page	1
Ending Page	5
File Size	676191
Page Count	5
File Format	PDF
ISBN	9781424457489
e-ISBN	9781424457502
DOI	10.1109/IDT.2009.5404147
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-15
Publisher Place	Saudi Arabia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Integrated circuit interconnections Cost function Capacitance Threshold voltage Inverters Dynamic voltage scaling Power dissipation Personal digital assistants Propagation delay
Content Type	Text
Resource Type	Article

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