NDLI: Test time reduction for scan-designed circuits by sliding compatibility

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Test time reduction for scan-designed circuits by sliding compatibility

Content Provider	IEEE Xplore Digital Library
Author	Jau-Shien Chang Chen-Shang Lin
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Jau-Shien Chang; Chen-Shang Lin)
Abstract	A post generation method for test time reduction of scan-designed circuits is developed in this paper. Maximum overlapping condition between consecutive applied patterns is identified. The application of the condition facilitated with the developed active sliding compatibility process significantly reduces the number of test clocks. It is demonstrated that the test clocks can be reduced by 50% on average from given test sets. Further evaluation shows that, for parity-scan, the test clocks required by our developed method are only 41% of those reported by H. Fujiwara and A. Yamamoto (1993).
Starting Page	330
Ending Page	335
File Size	639134
Page Count	6
File Format	PDF
ISBN	0818666900
DOI	10.1109/ATS.1994.367210
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-11-15
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Sequential analysis Clocks Circuit faults Flip-flops Switches Fault detection Test pattern generators Sequential circuits Costs
Content Type	Text
Resource Type	Article

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