NDLI: On-Chip Test Generation Mechanism for Scan-Based Two-Pattern Tests

Content Provider	IEEE Xplore Digital Library
Author	Nan-Cheng Lai Sying-Jyan Wang
Copyright Year	2008
Description	Author affiliation: Dept. of Comput. Sci., Nat. Chung-Hsing Univ., Taichung (Nan-Cheng Lai; Sying-Jyan Wang)
Abstract	We propose a new on-chip embedding mechanism to improve fault coverage in scan-based delay test. The initialization vector is shifted into the scan chain, and then the activation vector is generated by selectively inverting some bits to be loaded into the scan chain. Many scan-based delay test techniques do not provide good fault coverage as many valid test pattern pairs cannot be launched. The proposed approach provides a mechanism to modify activation vectors so that desired test pattern pairs can be launched. A formal design procedure for the embedded mechanism is presented. Experimental results show that, compared with previous work, the proposed method improves delay fault coverage with small area overhead.
Starting Page	251
Ending Page	256
File Size	312905
Page Count	6
File Format	PDF
ISBN	9780769533964
ISSN	10817735
DOI	10.1109/ATS.2008.46
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-24
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Circuit testing Logic testing Delay Lab-on-a-chip Automatic testing Clocks Hardware Test pattern generators Automatic logic units Delay fault Scan test
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Test Generation for Designs with On-Chip Clock Generators

Timing verification and delay test generation for hierarchical designs

Low hardware overhead scan based 3-weight weighted random BIST

Recursive Pseudo-Exhaustive Two-Pattern Generation

A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs

Constraint extraction for pseudo-functional scan-based delay testing

Transition test generation using replicate-and-reduce transform for scan-based designs

Memory efficient ATPG for path delay faults

Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture

On-Chip Test Generation Mechanism for Scan-Based Two-Pattern Tests

Similar Documents

Test Generation for Designs with On-Chip Clock Generators

Timing verification and delay test generation for hierarchical designs

Low hardware overhead scan based 3-weight weighted random BIST

Recursive Pseudo-Exhaustive Two-Pattern Generation

A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs

Constraint extraction for pseudo-functional scan-based delay testing

Transition test generation using replicate-and-reduce transform for scan-based designs

Memory efficient ATPG for path delay faults

Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture

On-Chip Test Generation Mechanism for Scan-Based Two-Pattern Tests