NDLI: A BIST architecture for FPGA look up table testing reduces reconfigurations

Content Provider	IEEE Xplore Digital Library
Author	Atoofian, E. Navabi, Z.
Copyright Year	2003
Description	Author affiliation: Electr. & Comput. Eng. Dept., Tehran Univ., Iran (Atoofian, E.; Navabi, Z.)
Abstract	This paper describes a test architecture for minimum number of test configurations for test of FPGA (field programmable gate array) LUTs (look up tables). Our test architecture includes a TPG (test pattern generator) that is tested while it is generating test data for LE (logic elements) that form our CUT (circuit under test). This scheme eliminates the need for switching LEs between CUT, TPG and ORA (output response analyzer) and having to perform many reconfigurations of the FPGA. An external ORA locates faults of the FPGA under test. In addition to the LUTs, we are also presenting a scheme for testing other parts of the LEs. Compared with other methods, our method uses the least number of reconfigurations of an FPGA for its LUT testing.
Sponsorship	IEEE Comput. Sci. Test Technol. Tech. Council
Starting Page	84
Ending Page	89
File Size	271401
Page Count	6
File Format	PDF
ISBN	0769519512
ISSN	10817735
DOI	10.1109/ATS.2003.1250788
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-11-16
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Integrated circuit testing Logic circuit testing Self-testing Table lookup
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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