NDLI: Implicit test generation for behavioral VHDL models

Content Provider	IEEE Xplore Digital Library
Author	Ferrandi, F. Fummi, F. Sciuto, D.
Copyright Year	1998
Description	Author affiliation: Dipt. di Elettronica e Inf., Politecnico di Milano, Italy (Ferrandi, F.)
Abstract	This paper proposes a behavioral-level test pattern generation algorithm for behavioral VHDL descriptions. The proposed approach is based on the comparison between the implicit description of the fault-free behavior and the faulty behavior, obtained through a new behavioral fault model. The paper will experimentally show that the test patterns generated at the behavioral level provide a very high stuck-at fault coverage when applied to different gate-level implementations of the given VHDL behavioral specification. Gate-level ATPGs applied on these same circuits obtain lower fault coverage, in particular when considering circuits with hard to detect faults.
Starting Page	587
Ending Page	596
File Size	1080023
Page Count	10
File Format	PDF
ISBN	0780350936
ISSN	10893539
DOI	10.1109/TEST.1998.743202
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-10-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Test pattern generators Circuit faults Circuit testing High level synthesis Logic testing Electronic design automation and methodology Automata Performance evaluation Guidelines Fault diagnosis
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Applied Mathematics

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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