NDLI: Geometric programming based power-delay optimization using transistor-sizing for submicron and deep submicron CMOS inverter

Content Provider	IEEE Xplore Digital Library
Author	Pattanaik, M. Banerjee, S.
Copyright Year	2003
Description	Author affiliation: Dept. of E & ECE, Indian Inst. of Technol., Kharagpur, India (Pattanaik, M.; Banerjee, S.)
Abstract	This paper proposes a new method to formulate the transistor sizing problem as a geometric programming by using a modified I-V model in the power-delay product (PDP), for sub micron and deep sub micron CMOS inverter circuits. The design objective and constraints are modeled as posynomial functions of the design variables. The model has been solved efficiently, which generates a number of important practical consequences. This method computes the absolute limit of performance for given input frequency and load capacitance of a transistor and technology parameters. The accuracy of performance prediction in the transistor-sizing (through geometric programming) problem is verified due to its closeness to SPICE simulation (0.25-/spl mu/m) results. Further the approach has been extended to predict the transistor sizing for deep submicron (0.09-/spl mu/m) CMOS inverter.
Sponsorship	IEEE Region 10
Starting Page	484
Ending Page	487
File Size	238838
Page Count	4
File Format	PDF
ISBN	0780381629
DOI	10.1109/TENCON.2003.1273369
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-10-15
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Inverters Semiconductor device modeling Solid modeling Circuits Frequency Capacitance CMOS technology Accuracy SPICE Computational modeling
Content Type	Text
Resource Type	Article

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