NDLI: Fast congestion-aware timing-driven placement for island FPGA

Content Provider	IEEE Xplore Digital Library
Author	Jinpeng Zhao Qiang Zhou Yici Cai
Copyright Year	2009
Description	Author affiliation: EDA Lab, Department of Computer Science, Tsinghua University, Beijing 100084, China (Jinpeng Zhao; Qiang Zhou; Yici Cai)
Abstract	A new fast timing-driven placement is presented in this paper, which is partitioning-based method, explicitly considering the congestion for island style FPGAs. The most distinct feature of this approach is that it not only reduces the circuit critical path delay efficiently, but also takes congestion into account. The harmony between partitioning objective and timing improvement goal is kept; moreover, the congestion constraint is added to cost function to improve routability in the meantime. As a result, it avoids the excessive usage of local routing resources while remaining circuit performance much better. The experimental results show our method, FCTP, is very fast. It is able to produce solutions with equal or better routability and up to average 8.19% improvement on performance but only less 1/3 average runtime compared to TVPR [1]. It also achieves much better results than PPFF [7] in terms of timing and congestion with negligible runtime penalty.
Starting Page	24
Ending Page	27
File Size	264858
Page Count	4
File Format	PDF
ISBN	9781424433414
DOI	10.1109/DDECS.2009.5012092
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-15
Publisher Place	Czech Republic
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Delay Runtime Timing Circuit optimization Electronic design automation and methodology Cost function Routing Assembly Optimization methods timing-driven placement FPGAs fast congestion-aware placement general alignment skill
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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