NDLI: Design aspects of a microprocessor data cache using 3D die interconnect technology

Content Provider	IEEE Xplore Digital Library
Author	Reed, P. Yeung, G. Black, B.
Copyright Year	2005
Description	Author affiliation: Microprocessor Res. Labs., Intel Corp., Austin, TX, USA (Reed, P.; Yeung, G.; Black, B.)
Abstract	This paper explores an implementation of a new technology called 3D die stacking. 3D die stacking is the bonding of two die either face-to-face or face-to-back in order to construct a 3D structure. In this work a face-to-face bonding is utilized because it yields a higher density die-to-die interconnect than is possible with face-to-back. With sufficiently dense die-to-die interconnect, devices as complex as an iA32 microprocessor can be repartitioned or split between two die in order to simultaneously improve performance and power. The 3D structure of this emerging technology is examined and applied in this paper to a conventional 2D 32KB data cache. In this study, it is shown that a 3D implementation can potentially improve the silicon area, complexity, performance and power of a 2D circuit simultaneously.
Sponsorship	IEEE Central Texas Sect. Japan Soc. of Appl. Phys
Starting Page	15
Ending Page	18
File Size	562040
Page Count	4
File Format	PDF
ISBN	0780390814
DOI	10.1109/ICICDT.2005.1502578
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microprocessors Stacking Bonding Integrated circuit interconnections Transistors Wires Manufacturing Costs CMOS technology Silicon
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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