NDLI: Multiple-clone configuration of relocatable partial bitstreams in Xilinx Virtex FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Ebrahim, A. Benkrid, K. Iturbe, X. Chuan Hong
Copyright Year	2013
Description	Author affiliation: Sch. of Eng., Univ. of Edinburgh, Edinburgh, UK (Ebrahim, A.; Benkrid, K.; Iturbe, X.; Chuan Hong)
Abstract	This paper addresses the high-performance systems which are based on swapping relocatable partial bitstreams (also called hardware tasks) in and out of an FPGA device using Dynamic Partial Reconfiguration (DPR) in Xilinx Virtex FPGAs. Configuration speed is important in such systems to achieve high performance. Previous research efforts were focused on over-clocking the Internal Configuration Access Port (ICAP) and compressing the partial bitstreams of the hardware tasks to enhance the configuration speed. We propose the use of the Multiple Frame Write (MFW) feature to significantly reduce the configuration time when multiple instances of a hardware task are needed. In this paper, we demonstrate the design and implementation of a novel internal reconfiguration engine which dynamically generates partial bitstreams required for simultaneous configuration of multiple clones of relocatable hardware tasks.
Starting Page	178
Ending Page	183
File Size	431050
Page Count	6
File Format	PDF
ISBN	9781467363839
DOI	10.1109/AHS.2013.6604243
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-24
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Field programmable gate arrays Cloning Engines Writing Synchronization Clocks Multiple Frame Write FPGA Dynamic Partial Reconfiguration
Content Type	Text
Resource Type	Article

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