NDLI: Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Velegalati, R. Kaps, J.-P.
Copyright Year	2011
Abstract	Implementations of mathematically secure cryptographic algorithms leak information through side channels during run time. Differential Power Analysis (DPA) attacks exploit power leakage to obtain the secret information. Dynamic and Differential Logic (DDL), one of the popular countermeasures against DPA attacks, tries to achieve constant power consumption thereby decor relating the leakage with the data being processed. Separated Dynamic and Differential Logic (SDDL), a variant of DDL, achieves this goal by duplicating the original design into Direct and Complementary parts which exhibit constant switching activity per clock cycle and have balanced net delays. Traditionally, on Field Programmable Gate Arrays (FPGAs) both parts are placed side-by-side to ensure symmetrical routing. However, due to process variations both parts will have slightly different delays. This limits the effectiveness of SDDL. In this paper we introduce a design flow to achieve interleaved placement of SDDL designs on Xilinx Spartan-3E FPGAs while preserving symmetric routing. We explore several placement configurations with respect to routing and security. The results of our experiments show that a well-balanced placement of SDDL can double the effectiveness of the SDDL countermeasures on FPGAs.
Starting Page	506
Ending Page	511
File Size	179334
Page Count	6
File Format	PDF
ISBN	9781457714849
DOI	10.1109/FPL.2011.100
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-05
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Routing Delay Registers Reactive power Logic gates Algorithm design and analysis Interleaved Placement SDDL for FPGAs Differential Power Analysis
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Improving security of sddl designs through interleaved placement on xilinx fpgas (2011)

Impact of dual placement on WDDL design security in Mesh-based and Tree-based FPGAs

Techniques to enable the use of Block RAMs on FPGAS with Dynamic and Differential Logic

An incremental placement and global routing algorithm for field-programmable gate arrays

Performance-directed retiming for FPGAs using post-placement delay information

A technology mapper for Xilinx FPGAs

Differential Power Analysis resistance of Camellia and countermeasure strategy on FPGAs

Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing

Implementing array multipliers in Xilinx FPGAs

Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs

Similar Documents

Improving security of sddl designs through interleaved placement on xilinx fpgas (2011)

Impact of dual placement on WDDL design security in Mesh-based and Tree-based FPGAs

Techniques to enable the use of Block RAMs on FPGAS with Dynamic and Differential Logic

An incremental placement and global routing algorithm for field-programmable gate arrays

Performance-directed retiming for FPGAs using post-placement delay information

A technology mapper for Xilinx FPGAs

Differential Power Analysis resistance of Camellia and countermeasure strategy on FPGAs

Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing

Implementing array multipliers in Xilinx FPGAs

Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs