NDLI: A Closed-Loop Architecture with Digital Output for Convective Accelerometers

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2008 IEEE Computer Society Annual Symposium on VLSI

Table of contents

Message from the General and Program Chairs

Symposium Committees

Adaptive Reliable Chips - Reconfigurable Computing in the Nano Era

Emerging Concepts in Non-volatile Memory Technologies - Era of Resistance Switching Memories

Arithmetic Data Path Optimization Using Borrow-Save Representation

Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design

Benchmarking Domain Specific Processors: A Case Study of Evaluating a Smart Card Processor Design

Determining the Optimal Number of Islands in Power Islands Synthesis

Defect Tolerance Inspired by Artificial Evolution

Reliability of n-Bit Nanotechnology Adder

Spintronic Device Based Non-volatile Low Standby Power SRAM

Application of Bottom-Up Methodology to RTW VCO

A Closed-Loop Architecture with Digital Output for Convective Accelerometers

A CMOS Multi-sensor System for 3D Orientation Determination

FSMD Partitioning for Low Power Using ILP

Uncriticality-Directed Low-Power Instruction Scheduling

Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices

BTB Access Filtering: A Low Energy and High Performance Design

A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications

System Level Design Space Exploration for Multiprocessor System on Chip

A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures

MPI-Based Adaptive Task Migration Support on the HS-Scale System

Low Power High Performance Digitally Assisted Pipelined ADC

A Novel Low-Power Clock Skew Compensation Circuit

High Speed Ultra Low Voltage CMOS inverter

A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection

Process Algebra Based SoC Test Scheduling for Test Time Minimization

Improving the Test of NoC-Based SoCs with Help of Compression Schemes

A Novel System on Chip (SoC) Test Solution

Testing Skew and Logic Faults in SoC Interconnects

A Programmable Frequency Divider in 0.18 um(micro-meter) CMOS Library

Energy Recovery from High-Frequency Clocks Using DC-DC Converters

Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL

Systematic HDL Design of a S-? Fractional-N Phase-Locked Loop for Wireless Applications

Impact of Technology Scaling on Digital Subthreshold Circuits

Low Standby Power and Robust FinFET Based SRAM Design

CMOS Control Enabled Single-Type FET NASIC

A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines

Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode Selection

Communication Centric Modelling of System on Chip Devices Targeting Multi-standard Telecommunication Applications

Performance Improvement of Physical Retiming with Shortcut Insertion

A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation

A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction

An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme

A Real Case of Significant Scan Test Cost Reduction

A Network Based Functional Verification Method of IEEE 1394a PHY Core

Cohesive Coverage Management for Simulation and Formal Property Verification

Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors

Memory Power Modeling - A Novel Approach

Integrated Power-Gating and State Assignment for Low Power FSM Synthesis

Efficient High-Level Power Estimation for Multi-standard Wireless Systems

Modeling and Optimization of Switching Power Dissipation in Static CMOS Circuits

Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture

SeReCon: A Secure Dynamic Partial Reconfiguration Controller

GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs

Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs

Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects

Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier

Characterisation of FPGA Clock Variability

A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing

Flow Maximization for NoC Routing Algorithms

Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-Chip

Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques

Adaptive Neuron Activation Function with FGMOS Based Operational Transconductance Amplifier

A Versatile Linear Insertion Sorter Based on a FIFO Scheme

Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection

Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations

Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory

Standard Cell Like Via-Configurable Logic Block for Structured ASICs

SDVM^R: A Scalable Firmware for FPGA-Based Multi-core Systems-on-Chip

Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning Scheme

FPGA-Based Circuit Model Emulation of Quantum Algorithms

Petri Net Based Rapid Prototyping of Digital Complex System

Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability

A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis

Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis

Efficient Realization of Strongly Indicating Function Blocks

Virtual Point-to-Point Links in Packet-Switched NoCs

Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip

A Web Server Based Edge Detector Implementation in FPGA

Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways

In Situ Design of Register Operations

An Efficient Motion Adaptive De-interlacing and Its VLSI Architecture Design

Raising the Level of Abstraction for the Timing Verification of System-on-Chips

Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture

Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement

Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions

NoC Power Estimation at the RTL Abstraction Level

Design of Fractal Image Compression on SOC

A Novel and Scalable RSA Cryptosystem Based on 32-Bit Modular Multiplier

A Neural Stimulator Output Stage for Dodecapolar Electrodes

Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects

Finding the Best Compromise in Compiling Compound Loops to Verilog

An Auto-adaptation Method for Dynamically Reconfigurable System-on-Chip

An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES

Compensating Algorithmic-Loop Performance Degradation in Asynchronous Circuits Using Hardware Multi-threading

A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)

IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

IEEE Computer Society Annual Symposium on VLSI

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002

A Closed-Loop Architecture with Digital Output for Convective Accelerometers

Content Provider	IEEE Xplore Digital Library
Author	Leman, O. Latorre, L. Mailly, F. Nouet, P.
Copyright Year	2008
Description	Author affiliation: LIRMM, Univ. Montpellier 2, Montpellier (Leman, O.; Latorre, L.; Mailly, F.; Nouet, P.)
Abstract	We study thermal convective accelerometers manufactured on a low-cost standard CMOS technology. As a closed-loop conditioning approach, we applied the thermal sigma-delta modulation principle to the readout of these sensors. This design leads to a simple architecture with minimized analog electronics. In this work, we consider the design of an improved sensor and analyze its properties. We show that quantization noise shaping is rather poor and analyze how it is influenced by the sensing cell design.
Starting Page	51
Ending Page	56
File Size	646405
Page Count	6
File Format	PDF
ISBN	9780769532912
DOI	10.1109/ISVLSI.2008.89
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-04-07
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Accelerometers Temperature sensors Bridge circuits Detectors Bridges Acceleration CMOS technology Delta-sigma modulation Mathematical model Thermal resistance sigma-delta MEMS CMOS accelerometer convective closed-loop
Content Type	Text
Resource Type	Article

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