NDLI: Multi-level buffer block planning and buffer insertion for large design circuits

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Multi-level buffer block planning and buffer insertion for large design circuits

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Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002

Multi-level buffer block planning and buffer insertion for large design circuits

Content Provider	IEEE Xplore Digital Library
Author	Jahanian, A. Zamani, M.S.
Copyright Year	2006
Description	Author affiliation: Dept. of IT & Comput. Eng., Amirkabir Univ. of Technol., Tehran (Jahanian, A.)
Abstract	Buffer insertion plays an increasingly critical role on circuit performance and signal integrity, especially in deep submicron region. Buffer insertion stage is very important for buffering efficiency. Early buffer insertion (e.g. at the floorplanning stage) may cause misestimation due to unknown cell locations, on the other hand buffer insertion after placement or during global routing may tend to be ineffective because the cell locations have been fixed and buffer resources may be distributed inappropriately. In this paper, a new method for buffer insertion is presented which inserts buffers during placement based on the planning of buffers at the floorplanning stage and congestion considerations. Experiments show that by our method, performance and congestion control are improved in large circuits including large amount of buffers
File Size	186092
File Format	PDF
ISBN	0769525334
DOI	10.1109/ISVLSI.2006.63
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-03-02
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Integrated circuit interconnections Transistors Delay Very large scale integration Circuit optimization Clocks Wire Path planning Process planning incremental placement Buffer planning buffer insertion
Content Type	Text
Resource Type	Article

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