NDLI: Decoder-based multi-context interconnect architecture

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Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002

Decoder-based multi-context interconnect architecture

Content Provider	IEEE Xplore Digital Library
Author	Lodi, A. Ciccarelli, L. Cappelli, A. Carnpi, F. Toma, M.
Copyright Year	2003
Description	Author affiliation: ARCES, Bologna Univ., Italy (Lodi, A.; Ciccarelli, L.; Cappelli, A.; Carnpi, F.; Toma, M.)
Abstract	Multi-context FPGAs are a convenient solution for run-time reconfiguration, but they suffer from large area occupation. This is mainly due to programmable interconnect configuration memories which need to be replicated as many times as the number of contexts. To overcome this limitation a new decoder-based interconnect architecture is proposed. Dramatic improvements in terms of area and delay with respect to previous approaches are presented, such that multi-context FPGAs can finally become a viable solution for next generation configurable devices.
Sponsorship	IEEE Comput. Soc. Tech. Committee on VLSI
Starting Page	231
Ending Page	233
File Size	251935
Page Count	3
File Format	PDF
ISBN	0769519040
DOI	10.1109/ISVLSI.2003.1183478
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-02-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Field programmable gate arrays Delay Switches Random access memory Runtime Wires Routing Reconfigurable logic Silicon
Content Type	Text
Resource Type	Article

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