NDLI: Pseudo-random behavioral ATPG

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Proceedings Ninth Great Lakes Symposium on VLSI

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Proceedings. Fifth Great Lakes Symposium on VLSI

Uniform area timing-driven circuit implementation

Optimization using implicit techniques for industrial designs

Optimal technology mapping for single output cells

A differential model approach to analog design automation

A new approach for modeling and optimization of analog systems

A scalable analog architecture for neural networks with on-chip learning and refreshing

Bus minimization and scheduling of multi-chip systems

Thumbnail rectilinear Steiner trees

A two-stage simulated annealing methodology

Optimizing wiring space in slicing floorplans

Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks

Design and analysis of a low-power energy-recovery adder

Coding a terminated bus for low power

Circuit/architecture for low-power high-performance 32-bit adder

Symbolic execution of data paths

Specification and synthesis of bounded indirection

Synthesis of SEU-tolerant ASICs using concurrent error correction

Scheduling conditional data-flow graphs with resource sharing

Automated verification of temporal properties specified as state machines in VHDL

Partitioning transition relations efficiently and automatically

Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functions

An efficient building block layout methodology for compact placement

Performance driven standard-cell placement using the genetic algorithm

An efficient heuristic approach on minimizing the number of feedthrough cells in standard cell placement

Priority driven channel pin assignment

A systolic algorithm and architecture for image thinning

Analyzing and verifying locally clocked circuits with the concurrency workbench

Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs

A local clocking approach for self-timed datapath designs

A soft computing approach to hardware software codesign

Technology mapping algorithms for sequential circuits using look-up table based FPGAS

Modeling of communication protocols in VHDL

Using EDIF for software generation

A protocol extraction strategy for control point insertion in design for test of transition signaling circuits

Statistical estimation of delay fault detectabilities and fault grading

Test application time reduction for scan based sequential circuits

Pseudo-random behavioral ATPG

Fast algorithm for performance-oriented Steiner routing

On locally optimal breaking of nondisjoint cyclic vertical constraints in VLSI channel routing

OPRON: a new approach to planar OTC routing

Parallel hierarchical global routing for general cell layout

Improving self-timed pipeline ring performance through the addition of buffer loops

Scan testing of asynchronous sequential circuits

A new look at the conditions for the synthesis of speed-independent circuits

Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT

Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test

Linking fabrication and parametric testing to VLSI design courses

A personal computer based VLSI design curriculum

A scalable shared buffer ATM switch architecture

ATM burst traffic generator

A universal formalization of the effects of threshold voltages for discrete switch-level circuit models

Index of authors

Proceedings of 4th Great Lakes Symposium on VLSI

[1993] Proceedings Third Great Lakes Symposium on VLSI-Design Automation of High Performance VLSI Systems

[1992] Proceedings of the Second Great Lakes Symposium on VLSI

[1991] Proceedings. First Great Lakes Symposium on VLSI

Pseudo-random behavioral ATPG

Content Provider	IEEE Xplore Digital Library
Author	Courbis, A.-L. Santucci, J.-F.
Copyright Year	1995
Description	Author affiliation: LG12P, EMA-EERIE, Nimes, France (Courbis, A.-L.; Santucci, J.-F.)
Abstract	This paper deals with a new approach for the Automatic Test Pattern Generation (ATPG) of circuits described from a behavioral point of view in VHDL. This approach is based on a pseudo-random process characterized by the fact that criteria for computing the test length and evaluating the quality of the generated data come from the field of software engineering. This paper presents the bases of this new approach in the field of hardware engineering and some experimental results.
Starting Page	192
Ending Page	195
File Size	395530
Page Count	4
File Format	PDF
ISBN	0818670355
ISSN	10661395
DOI	10.1109/GLSV.1995.516051
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-03-16
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic test pattern generation Circuit testing Test pattern generators Circuit faults Software testing Random number generation Fault detection Software engineering Hardware Electrical fault detection
Content Type	Text
Resource Type	Article

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