NDLI: Capacitive Coupling Mitigation for TSV-based 3D ICs

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2015 IEEE 33rd VLSI Test Symposium (VTS)

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Fault diagnosis for flow-based microfluidic biochips

Rapid online fault recovery for cyber-physical digital microfluidic biochips

Fault modeling and testing of 1T1R memristor memories

A low cost jitter separation and characterization method

Ultrafast stimulus error removal algorithm for ADC linearity test

Disturbance-free BIST for loop characterization of DC-DC buck converters

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TMO: A new class of attack on cipher misusing test infrastructure

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Impact of parameter variations on FinFET faults

Memory repair for high defect densities

Horizontal-FPN fault coverage improvement in production test of CMOS imagers

Capacitive Coupling Mitigation for TSV-based 3D ICs

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Resiliency challenges in sub-10nm technologies

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MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM array

An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging

Integral impact of BTI and voltage temperature variation on SRAM sense amplifier

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Scalability study of PSANDE: Power supply analysis for noise and delay estimation

Robust counterfeit PCB detection exploiting intrinsic trace impedance variations

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Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects

Test vector omission with minimal sets of simulated faults

Test compaction by test cube merging for four-way bridging faults

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Capacitive Coupling Mitigation for TSV-based 3D ICs

Content Provider	IEEE Xplore Digital Library
Author	Eghbal, A. Yaghini, P.M. Bagherzadeh, N.
Copyright Year	2015
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Irvine, Irvine, CA, USA (Eghbal, A.; Yaghini, P.M.; Bagherzadeh, N.)
Abstract	TSV-to-TSV capacitive coupling has large disruptive effects on timing requirements of the circuit. The latency effect of TSV-to-TSV capacitive coupling for different characteristics of a TSV using circuit-level model is presented in this article. Two coding approaches are proposed to mitigate capacitive parasitic effects by adjusting the current flow pattern for any given n × n mesh of TSV arrangement to reduce the number of 8C/7C parasitic capacitance. The experimental results proves the efficacy of the proposed coding methods.
Starting Page	1
Ending Page	6
File Size	430707
Page Count	6
File Format	PDF
ISBN	9781479975976
DOI	10.1109/VTS.2015.7116279
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-04-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Encoding Through-silicon vias Parasitic capacitance Couplings Three-dimensional displays Arrays Receivers
Content Type	Text
Resource Type	Article

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