NDLI: Design and optimization of multi-level TAM architectures for hierarchical SOCs

Please wait, while we are loading the content...

2015 IEEE 33rd VLSI Test Symposium (VTS)

2014 IEEE 32nd VLSI Test Symposium (VTS)

2013 IEEE 31st VLSI Test Symposium (VTS)

2012 IEEE 30th VLSI Test Symposium (VTS)

29th VLSI Test Symposium

2010 28th VLSI Test Symposium (VTS)

2009 27th IEEE VLSI Test Symposium

26th IEEE VLSI Test Symposium (vts 2008)

25th IEEE VLSI Test Symposium (VTS'07)

24th IEEE VLSI Test Symposium

23rd IEEE VLSI Test Symposium (VTS'05)

22nd IEEE VLSI Test Symposium, 2004. Proceedings.

Proceedings. 21st VLSI Test Symposium, 2003.

Proceedings 21st IEEE VLSI Test Symposium

Keynote Address

Building yield into systems-on chips for nanometer technologies

VTS'02 Best Panel Award

VTS'02 Best Paper Award

A reconfigurable shared scan-in architecture

Test data compression and test time reduction of longest-path-per-gate tests based on Illinois scan architecture

Transition test generation using replicate-and-reduce transform for scan-based designs

Use of multiple I/sub DDQ/ test metrics for outlier identification

Effectiveness comparisons of outlier screening methods for frequency dependent defects on complex ASICs

Effectiveness of I-V testing in comparison to IDDq tests [IC testing]

High speed ring generators and compactors of test data [logic IC test]

Built-in reseeding for serial BIST

BIST reseeding with very few seeds

Ultra low cost analog BIST using spectral analysis

DSP-based statistical self test of on-chip converters

High coverage analog wafer-probe test design and co-optimization with assembled-package test to minimize overall test cost

Analysis and design of optimal combinational compactors [logic test]

Application of Saluja-Karpovsky compactors to test responses with many unknowns

Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression

Eliminating non-determinism during test of high-speed source synchronous differential buses

The impact of NoC reuse on the testing of core-based systems

Automatic configuration generation for FPGA interconnect testing

Threshold voltage mismatch (/spl Delta/V/sub T/) fault modeling

Test generation for maximizing ground bounce considering circuit delay

Testing SoC interconnects for signal integrity using boundary scan

On maximizing the fault coverage for a given test length limit in a synchronous sequential circuit

An efficient test relaxation technique for synchronous sequential circuits

Path-delay fault simulation for circuits with large numbers of paths for very large test sets

1149.4 based on-line quiescent state monitoring technique [analog DFT]

Measurement of phase and frequency variations in radio-frequency signals

An analog checker with dynamically adjustable error threshold for fully differential circuits

Test data compression using dictionaries with fixed-length indices [SOC testing]

Deterministic test vector decompression in software using linear operations [SOC testing]

Efficient seed utilization for reseeding based compression [logic testing]

Detecting intra-word faults in word-oriented memories

Test and diagnosis of word-oriented multiport memories

Generating complete and optimal march tests for linked faults in memories

Energy-efficient logic BIST based on state correlation analysis

Power constrained test scheduling with dynamically varied TAM

Development of energy consumption ratio test

Design for consecutive transparency of cores in system-on-a-chip

An embedded autonomous scan-based results analyzer (EARA) for SoC cores

Design and optimization of multi-level TAM architectures for hierarchical SOCs

Test consideration for nanometer scale CMOS circuits

Test resource partitioning and optimization for SOC designs

SOC test scheduling using simulated annealing

Layered approach to designing system test interfaces

Diagnosis of delay defects using statistical timing models

Improving diagnostic resolution of delay faults using path delay fault model

Concurrent execution of diagnostic fault simulation and equivalence identification during diagnostic test generation

BIST-aided scan test - a new method for test cost reduction

Built-in TPG with designed phaseshifts

A test interface for built-in test of non-isolated scanned cores

A circuit level fault model for resistive opens and bridges

Analyzing crosstalk in the presence of weak bridge defects

Efficient implication-based untestable bridge fault identifier

Testable design and testing of micro-electro-fluidic arrays

Fault testing for reversible circuits

Design for self-checking and self-timed datapath

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)

Proceedings 19th IEEE VLSI Test Symposium. VTS 2001

Proceedings 18th IEEE VLSI Test Symposium

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125)

Proceedings of 14th VLSI Test Symposium

Proceedings 13th IEEE VLSI Test Symposium

Proceedings of IEEE VLSI Test Symposium

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium

Digest of Papers. 1992 IEEE VLSI Test Symposium

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

Design and optimization of multi-level TAM architectures for hierarchical SOCs

Content Provider	IEEE Xplore Digital Library
Author	Iyengar, V. Chakrabarty, K. Krasniewski, M.D. Kumar, G.N.
Copyright Year	2003
Description	Author affiliation: IBM Microeletronics, Essex Junction, VT, USA (Iyengar, V.)
Abstract	Multi-level TAM optimization is necessary for modular testing of hierarchical SOCs that contain older-generation SOCs as embedded cores. We present two hierarchical TAM optimization flows that exploit recent advances in TAM design for flattened SOC hierarchies. Unlike prior methods that assume flat test hierarchies, the proposed methods are directly applicable to real-world design transfer models between the core vendor and the SOC integrator. Experimental results are presented for four ITC'02 SOC test benchmarks.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	299
Ending Page	304
File Size	330824
Page Count	6
File Format	PDF
ISBN	0769519245
ISSN	10930167
DOI	10.1109/VTEST.2003.1197667
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-05-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design optimization System testing Logic testing Computer architecture Microelectronics Embedded computing Design engineering Benchmark testing System-on-a-chip Costs
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in