NDLI: A self-test methodology for IP cores in bus-based programmable SoCs

Content Provider	IEEE Xplore Digital Library
Author	Jing-Reng Huang Iyer, M.K. Kwang-Ting Cheng
Copyright Year	2001
Description	Author affiliation: Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA (Jing-Reng Huang)
Abstract	We present a novel test methodology for testing IP cores in SoCs with embedded processor cores. A test program is run on the processor core that generates and delivers test patterns to the target IP cores in the SoC and analyzes the test responses. This provides tremendous flexibility in the type of patterns that can be applied to the IP cores without incurring significant hardware overhead. We use a bus based SoC simulation model to validate our test methodology. The test methodology involves addition of a test wrapper that can be configured for specific test needs. The methodology supports at-speed testing for delay faults and stuck-at testing of IP cores implementing full-scan.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	198
Ending Page	203
File Size	576865
Page Count	6
File Format	PDF
ISBN	0769511228
DOI	10.1109/VTS.2001.923439
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-04-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test System-on-a-chip Circuit testing Automatic testing Test pattern generators Delay Software testing Embedded software Pattern analysis System testing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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