NDLI: A fault simulation based test pattern generator for synchronous sequential circuits

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A fault simulation based test pattern generator for synchronous sequential circuits

Content Provider	IEEE Xplore Digital Library
Author	Ruifeng Guo Pomeranz, I. Reddy, S.M.
Copyright Year	1999
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA (Ruifeng Guo)
Abstract	We describe a fault simulation based test generation procedure for synchronous sequential circuits. Several techniques are used to generate test sequences to achieve high fault coverages at low computational complexity. Experimental results presented demonstrate that the proposed procedure achieves fault coverages which are in all cases the same or higher than those achieved by existing procedures. The run times of the procedure are considerably smaller compared to the existing procedures.
Starting Page	260
Ending Page	267
File Size	255573
Page Count	8
File Format	PDF
ISBN	076950146X
ISSN	10930167
DOI	10.1109/VTEST.1999.766674
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-04-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Circuit simulation Test pattern generators Sequential circuits Circuit testing Sequential analysis Computational modeling Synchronous generators Logic testing Genetics
Content Type	Text
Resource Type	Article

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