NDLI: Sub-100 nm CMOS/SIMOX delay modeling by time-dependent gate capacitance model

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1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers

International Symposium on VLSI Technology, Systems and Applications,

Sub-100 nm CMOS/SIMOX delay modeling by time-dependent gate capacitance model

Content Provider	IEEE Xplore Digital Library
Author	Lee, M. Asada, K.
Copyright Year	1993
Description	Author affiliation: Dept. of Electron. Eng., Tokyo, Japan (Lee, M.; Asada, K.)
Abstract	Contribution of the time-dependent gate capacitance (TDGC) model to CMOS/SIMOX inverter propagation delay time (TPD) in the deep sub-micrometer gate is studied. Results of theoretical prediction are compared with measurements of fifty-one stage ring oscillator TPDs. The TDGC model extends over conventional models in terms of worst- and best-case TPDs. It is predicted that the TDGC effect in the deep submicrometer regime will dominate when parasitic capacitances become relatively small as in future SOI technology.
Starting Page	242
Ending Page	246
File Size	377580
Page Count	5
File Format	PDF
ISBN	0780309782
DOI	10.1109/VTSA.1993.263597
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-05-12
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling Parasitic capacitance Inverters MOS devices Propagation delay Delay effects MOSFET circuits Voltage Semiconductor films Time measurement
Content Type	Text
Resource Type	Article

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